US2015250056A1PendingUtilityA1

Printed circuit board

Assignee: IBIDEN CO LTDPriority: Sep 2, 1999Filed: May 18, 2015Published: Sep 3, 2015
Est. expirySep 2, 2019(expired)· nominal 20-yr term from priority
H10W 90/724H10W 72/9415H10W 72/9223H10W 72/942H10W 72/923H10W 72/90H10W 70/655H10W 70/63H10W 70/60H10W 90/00H10W 72/00H10W 70/685H10W 70/635H10W 70/05H10W 44/601H10W 44/501H05K 2201/10015H05K 2201/10636H01G 4/224H01G 4/40H05K 1/181H01G 4/248H05K 1/112H05K 1/0231H01G 2/06H01G 4/228H05K 3/4602H05K 2201/10674H05K 1/115H05K 2201/09509H05K 1/183H05K 1/186H01G 4/12H05K 1/185H05K 2201/096H05K 2201/09545Y02P70/50H05K 3/18
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Claims

Abstract

A printed circuit board includes a substrate having an opening portion, a chip capacitor device accommodated in the opening portion of the substrate, and a buildup structure formed on the substrate such that the buildup structure covers the chip capacitor device in the opening portion of the substrate. The chip capacitor has a dielectric body having a surface facing the buildup structure, first electrodes formed on the surface of the dielectric body and second electrodes formed on the surface of the dielectric body, and the buildup structure has first via structures and second via structures such that the first via structures are connected to the first electrodes, respectively, and the second via structures are connected to the second electrodes, respectively.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A printed circuit board, comprising:
 a substrate having an opening portion;   a chip capacitor device accommodated in the opening portion of the substrate; and   a buildup structure formed on the substrate such that the buildup structure covers the chip capacitor device in the opening portion of the substrate,   wherein the chip capacitor device has a dielectric body having a surface facing the buildup structure, a plurality of first electrodes formed on the surface of the dielectric body and a plurality of second electrodes formed on the surface of the dielectric body, and the buildup structure has a plurality of first via structures and a plurality of second via structures such that the first via structures are connected to the first electrodes, respectively, and the second via structures are connected to the second electrodes, respectively.   
     
     
         2 . The printed circuit board according to  claim 1 , wherein each of the first electrodes has a copper plated film on a surface thereof, and each of the second electrodes has a copper plated film on a surface thereof. 
     
     
         3 . The printed circuit board according to  claim 1 , wherein each of the first via structures comprises plated copper material, and each of the second via structures comprises plated copper material. 
     
     
         4 . The printed circuit board according to  claim 1 , further comprising a second chip capacitor device accommodated in the opening portion of the substrate, wherein the second chip capacitor device has a dielectric body having a surface facing the buildup structure, a plurality of first electrodes formed on the surface of the dielectric body and a plurality of second electrodes formed on the surface of the dielectric body. 
     
     
         5 . The printed circuit board according to  claim 1 , wherein the opening portion of the substrate is a penetrating opening portion formed through the substrate. 
     
     
         6 . The printed circuit board according to  claim 1 , wherein the buildup structure is configured to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor device. 
     
     
         7 . The printed circuit board according to  claim 1 , wherein the substrate is a core substrate comprising resin. 
     
     
         8 . The printed circuit board according to  claim 1 , wherein each of the first via structures comprises a stacked via structure comprising a plurality of via structures formed on one another such that the stacked via structure is connected to a respective one of the first electrodes of the chip capacitor through the buildup structure, and each of the second via structures comprises a stacked via structure comprising a plurality of via structures formed on one another such that the stacked via structure is connected to a respective one of the second electrodes of the chip capacitor through the buildup structure. 
     
     
         9 . The printed circuit board according to  claim 4 , wherein the buildup structure is configured to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor device and the second chip capacitor device. 
     
     
         10 . The printed circuit board according to  claim 1 , wherein each of the first via structures comprises a stacked via structure comprising a plurality of filled via structures formed directly on one another such that the stacked via structure is connected to a respective one of the first electrodes of the chip capacitor through the buildup structure, and each of the second via structures comprises a stacked via structure comprising a plurality of filled via structures formed directly on one another such that the stacked via structure is connected to a respective one of the second electrodes of the chip capacitor through the buildup structure. 
     
     
         11 . The printed circuit board according to  claim 1 , wherein each of the first and second electrodes has a plated film formed by plating, each of the first and second via structures includes a plated layer formed by plating, and the plated layer of each of the first and second via structures is directly connected to the plated film of each of the first and second electrodes. 
     
     
         12 . The printed circuit board according to  claim 1 , wherein the buildup structure has a plurality of mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor device, and the first and second via structures are connecting the mounting conductor structures and the first and second electrodes through the buildup structure. 
     
     
         13 . The printed circuit board according to  claim 1 , wherein the buildup structure includes a plurality of insulating layers comprising resins, respectively, and a plurality of conductor circuit layers formed on the plurality of insulating layers, respectively. 
     
     
         14 . The printed circuit board according to  claim 1 , wherein the buildup structure includes a plurality of insulating layers comprising resins, respectively, and a plurality of conductor circuit layers formed on the plurality of insulating layers, respectively, and the first and second via structures are formed through the insulating layers. 
     
     
         15 . The printed circuit board according to  claim 4 , wherein the opening portion of the substrate is a penetrating opening portion formed through the substrate. 
     
     
         16 . The printed circuit board according to  claim 2 , wherein each of the first via structures comprises plated copper material, and each of the second via structures comprises plated copper material. 
     
     
         17 . The printed circuit board according to  claim 12 , wherein the mounting conductor structures comprise bumps comprising conductive materials, respectively. 
     
     
         18 . The printed circuit board according to  claim 1 , wherein the substrate has a thickness which is substantially equal to a thickness of the chip capacitor device and comprises a core substrate comprising an insulating material. 
     
     
         19 . The printed circuit board according to  claim 5 , wherein the substrate has a thickness which is substantially equal to a thickness of the chip capacitor device and comprises a core substrate comprising an insulating material. 
     
     
         20 . The printed circuit board according to  claim 1 , wherein the substrate comprises a core substrate having a thickness which is substantially equal to a thickness of the chip capacitor device, and the buildup structure includes a plurality of insulating layers comprising resins, respectively, and a plurality of conductor circuit layers formed on the plurality of insulating layers, respectively, and the first and second via structures are formed through the insulating layers, respectively.

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