Buried-channel field-effect transistors

Abstract

Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.

What is claimed is: 
     
         1 . A method for forming a buried-channel field-effect transistor (FET), comprising:
 forming a dummy gate on a substrate;   depositing dielectric material around the dummy gate;   doping source and drain regions on the substrate with a dopant having a first type;   removing the dummy gate;   growing a doped shielding layer on the substrate in a channel region after removal of the dummy gate, said doped shielding layer having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region, wherein the doped shielding layer is formed after the source and drain regions are doped;   forming a gate dielectric over the doped shielding layer; and   forming a gate on the gate dielectric.   
     
     
         2 . The method of  claim 1 , wherein the doped shielding layer at least partially overlaps the source and drain regions. 
     
     
         3 . The method of  claim 1 , wherein the doped shielding layer is formed from in-situ boron-doped silicon germanium. 
     
     
         4 . The method of  claim 1 , wherein the doped shielding layer includes a boron dopant concentration of about 5·10 19 /cm 3 . 
     
     
         5 . The method of  claim 1 , wherein forming the dummy gate further comprises:
 forming a dummy gate dielectric on the substrate;   depositing dummy gate material over the substrate and the dummy gate dielectric;   forming a dummy gate mask to delineate an area for the dummy gate;   etching the dummy gate material around the dummy gate area using an anisotropic etch; and   removing the dummy gate mask.   
     
     
         6 . The method of  claim 1 , wherein the dummy gate at least partially overlaps the source and drain regions. 
     
     
         7 . The method of  claim 1 , further comprising forming raised source and drain regions on at least a portion of the source and drain regions. 
     
     
         8 . The method of  claim 1 , wherein the substrate is a bulk semiconductor. 
     
     
         9 . The method of  claim 1 , wherein the substrate is a semiconductor-on-insulator substrate. 
     
     
         10 . The method of  claim 1 , wherein the dielectric is a high-k dielectric. 
     
     
         11 . The method of  claim 1 , wherein the doped shielding layer is formed on an area of the substrate exposed by the removal of the dummy gate.