Semiconductor memory device and method for manufacturing same

Abstract

According to one embodiment, a semiconductor memory device includes a semiconductor member, a first insulating layer provided on the semiconductor member, a TaN layer provided on the first insulating layer and containing tantalum and nitrogen, a TaSiN layer provided on the TaN layer in contact with the TaN layer and containing tantalum, silicon, and nitrogen, a second insulating layer provided on the TaSiN layer in contact with the TaSiN layer and containing oxygen, and a control electrode provided on the second insulating layer.

1 - 17 . (canceled) 
     
     
         18 . A method for manufacturing a semiconductor memory device, comprising:
 depositing a TaN layer containing tantalum and nitrogen on a first insulating layer provided on a semiconductor member;   depositing a SiN layer containing silicon and nitrogen on the TaN layer;   depositing a SiO layer containing silicon and oxygen on the SiN layer;   forming a TaSiN layer containing tantalum, silicon and nitrogen between the TaN layer and the SiO layer by heat treatment; and   forming a control electrode on the SiO layer.   
     
     
         19 . The method according to  claim 18 , wherein the heat treatment is performed in a nitrogen atmosphere. 
     
     
         20 . The method according to  claim 18 , wherein in the heat treatment, tantalum in the TaN layer is diffused into the SiN layer. 
     
     
         21 . The method according to  claim 18 , further comprising:
 depositing a silicon layer containing silicon on the first insulating layer before depositing the TaN layer.   
     
     
         22 . The method according to  claim 21 , further comprising:
 depositing a TaO layer containing tantalum and oxygen on the silicon layer before depositing the TaN layer.   
     
     
         23 . The method according to  claim 18 , further comprising:
 depositing a metal oxide layer on the SiO layer before forming the control electrode.   
     
     
         24 . The method according to  claim 18 , further comprising:
 depositing a metal oxide layer on the SiO layer before forming the control electrode, the metal oxide layer containing an oxide of one or more elements selected from the group consisting of silicon, hafnium and aluminum.   
     
     
         25 . A method for manufacturing a semiconductor memory device, comprising:
 forming a stack of a TaN layer, a SiN layer, and a SiO layer in this order, the TaN layer containing tantalum and nitrogen, the SiN layer containing silicon and nitrogen, and the SiO layer containing silicon and oxygen; and   performing heat treatment thereby diffusing the tantalum in the TaN layer into the SiN layer,   wherein, in the stack, the TaN layer is provided on a side of a semiconductor member and the SiO layer is provided on a side of a control electrode.   
     
     
         26 . The method according to  claim 25 , wherein the heat treatment is performed in a nitrogen atmosphere. 
     
     
         27 . The method according to  claim 25 , wherein the stack further has a silicon layer provided between the semiconductor member and the TaN layer. 
     
     
         28 . The method according to  claim 27 , wherein the stack further has a TaO layer provided between the silicon layer and the TaN layer, and the TaO layer contains tantalum and oxygen. 
     
     
         29 . The method according to  claim 25 , wherein the stack further has a metal oxide layer provided between the SiO layer and the control electrode. 
     
     
         30 . The method according to  claim 25 , wherein the stack further has a metal oxide layer provided between the SiO layer and the control electrode, and the metal oxide layer contains an oxide of one or more elements selected from the group consisting of silicon, hafnium and aluminum. 
     
     
         31 . A method for manufacturing a semiconductor memory device, comprising:
 forming a Ta-containing layer containing tantalum, silicon and nitrogen; and   performing heat treatment,   wherein, in a concentration profile indicating relationship between vertical position in the Ta-containing layer and concentration of each element after the performing heat treatment, a silicon peak and a nitrogen peak are located inside a tantalum peak.   
     
     
         32 . The method according to  claim 31 , wherein the heat treatment is performed in a nitrogen atmosphere. 
     
     
         33 . The method according to  claim 31 , wherein the silicon peak and the nitrogen peak are located in an end portion on the control electrode side of the tantalum peak. 
     
     
         34 . The method according to  claim 31 , wherein
 the device has an insulating layer provided between the Ta-containing layer and the control gate, and a portion on the Ta-containing layer side of the insulating layer is made of silicon oxide.   
     
     
         35 . The method according to  claim 31 , wherein
 the device has an insulating layer provided between the Ta-containing layer and the control gate, the insulating layer contains nitrogen, and nitrogen concentration of a portion on the Ta-containing layer side of the insulating layer is higher than nitrogen concentration of a portion on the control electrode side of the insulating layer.   
     
     
         36 . The method according to  claim 31 , wherein
 the device has an insulating layer provided between the Ta-containing layer and the control gate, and the insulating layer contains an oxide of one or more elements selected from the group consisting of hafnium and aluminum.   
     
     
         37 . The method according to  claim 31 , wherein
 the device has an insulating layer provided between the Ta-containing layer and the control gate, and   the Ta-containing layer and the insulating layer are formed by stacking at least a SiN layer containing silicon and nitrogen and a SiO layer containing silicon and oxygen in this order on a TaN layer containing tantalum and nitrogen, before the heat treatment.