Memory Cells and Methods Of Forming Memory Cells

Abstract

A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.

1 . A memory cell comprising:
 a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel; and   a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between, one of the capacitor electrodes comprising the channel or being electrically coupled to the channel other than through either of the source/drains, the other of the capacitor electrodes comprising a portion of the body other than the channel, the capacitor dielectric having an elevationally outer surface that is directly against a base of at least one of the source/drains.   
     
     
         2 . (canceled) 
     
     
         3 . The memory cell of  claim 1  wherein the channel is horizontally oriented, the gate construction being above the channel. 
     
     
         4 . The memory cell of  claim 1  wherein the other capacitor electrode comprises conductivity modifying dopant of the same type and of the same concentration as that of the channel. 
     
     
         5 . The memory cell of  claim 1  wherein the one capacitor electrode is the channel. 
     
     
         6 . The memory cell of  claim 1  wherein the one capacitor electrode is electrically coupled to the channel. 
     
     
         7 . The memory cell of  claim 6  wherein the one capacitor electrode comprises conductivity modifying dopant of the same type and of the same concentration as that of the channel. 
     
     
         8 . The memory cell of  claim 7  wherein the other capacitor electrode comprises conductivity modifying dopant of the same type and of the same concentration as that of the channel. 
     
     
         9 . The memory cell of  claim 6  wherein the one capacitor electrode comprises conductivity modifying dopant of the same type as that of the channel and of different concentration from that of the channel. 
     
     
         10 . The memory cell of  claim 9  wherein the conductivity modifying dopant of the one capacitor electrode is of higher concentration from that of the channel. 
     
     
         11 . The memory cell of  claim 6  wherein the channel and the one capacitor electrode are of the same composition. 
     
     
         12 . The memory cell of  claim 6  wherein the channel and the one capacitor electrode are of different compositions relative one another. 
     
     
         13 . The memory cell of  claim 12  wherein the channel is substantially monocrystalline and the one capacitor electrode is substantially polycrystalline. 
     
     
         14 . The memory cell of  claim 12  wherein each of the channel and the one capacitor electrode comprises doped silicon. 
     
     
         15 . The memory cell of  claim 6  wherein both of the source/drains are directly against the capacitor dielectric and directly against the one capacitor electrode. 
     
     
         16 . The memory cell of  claim 6  wherein,
 the channel is horizontally oriented; 
 the gate construction is above the channel; and 
 the one capacitor electrode is below the channel. 
 
     
     
         17 . The memory cell of  claim 6  wherein the capacitor dielectric is V-shaped in lateral cross-section. 
     
     
         18 - 19 . (canceled) 
     
     
         20 . The memory cell of  claim 1  wherein the capacitor dielectric is directly against both of the source/drains. 
     
     
         21 . (canceled) 
     
     
         22 . The memory cell of  claim 1  wherein the channel is directly against the capacitor dielectric. 
     
     
         23 . The memory cell of  claim 1  wherein the one capacitor electrode is directly against each of the pair of source/drains. 
     
     
         24 . The memory cell of  claim 1  wherein the one capacitor electrode is not directly against either of the pair of source/drains. 
     
     
         25 . The memory cell of  claim 1  wherein the memory cell comprises a data/sense line electrically coupled to one of the source/drains. 
     
     
         26 . The memory cell of  claim 1  wherein the memory cell comprises a reference voltage line other than a data/sense line electrically coupled to one of the source/drains. 
     
     
         27 . The memory cell of  claim 1  wherein the memory cell comprises a data/sense line electrically coupled to one of the source/drains and a reference voltage line other than the data/sense line electrically coupled to the other of the source/drains. 
     
     
         28 . A method of forming a memory cell comprising a transistor device and a capacitor, the method comprising:
 lining an opening in first semiconductor material with capacitor dielectric;   forming second semiconductor material within the opening over the capacitor dielectric and over the first semiconductor material outside of the opening, the second semiconductor material within the opening comprising one capacitor electrode of the memory cell capacitor, the first semiconductor material under the capacitor dielectric comprising another capacitor electrode of the memory cell capacitor;   forming a channel and source/drains of the memory cell transistor with the second semiconductor material; and   forming a gate construction of the memory cell transistor operatively proximate the channel.   
     
     
         29 . The method of  claim 28  wherein the first and second semiconductor materials comprise silicon. 
     
     
         30 . The method of  claim 28  wherein forming the second semiconductor material comprises epitaxial growth. 
     
     
         31 . A method of forming a memory cell comprising a transistor device and a capacitor, the method comprising:
 lining an opening in first semiconductor material with capacitor dielectric;   forming second semiconductor material within the opening over the capacitor dielectric, the second semiconductor material within the opening comprising one of the capacitor electrodes of the memory cell capacitor, the first semiconductor material under the capacitor dielectric comprising another capacitor electrode of the memory cell capacitor;   forming third semiconductor material over the second semiconductor material to comprise a channel of the memory cell transistor;   forming source/drain regions of the memory cell transistor with at least one of the first and third semiconductor materials; and   forming a gate construction of the memory cell transistor operatively proximate the channel.   
     
     
         32 . The method of  claim 31  comprising forming the source/drain regions with the third semiconductor material. 
     
     
         33 . The method of  claim 32  comprising forming the source/drain regions with the first semiconductor material. 
     
     
         34 . The method of  claim 31  wherein the first, second, and third semiconductor materials comprise silicon. 
     
     
         35 . The method of  claim 34  wherein the first and third semiconductor materials comprise substantially monocrystalline silicon and the second semiconductor material comprises substantially polycrystalline silicon. 
     
     
         36 . The method of  claim 31  wherein the second semiconductor material comprises substantially polycrystalline silicon and forming the third semiconductor material comprises epitaxially growing substantially monocrystalline silicon. 
     
     
         37 . A memory cell comprising:
 a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel; and   a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between, one of the capacitor electrodes comprising the channel or being electrically coupled to the channel, the other of the capacitor electrodes comprising a portion of the body other than the channel, the capacitor dielectric has laterally separated elevationally outer surfaces that are individually directly against a base different ones of the source/drains.   
     
     
         38 . The memory cell of  claim 37  wherein the one capacitor electrode is electrically coupled to the channel other than through either of the source/drains. 
     
     
         39 . The memory cell of  claim 38  wherein the one capacitor electrode is underneath the gate construction. 
     
     
         40 . The memory cell of  claim 39  wherein the one capacitor electrode is electrically coupled to the channel other than through either of the source/drains.