Semiconductor chips having a dual-layered structure, packages having the same, and methods of fabricating the semiconductor chips and the packages

Abstract

Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.

What is claimed is: 
     
         1 . A method of fabricating a dual-layered structural semiconductor chip, the method comprising:
 providing a first semiconductor chip including a first substrate having a first top surface and a first bottom surface opposite to each other and a first active layer disposed on the first top surface;   providing a second semiconductor chip including a second substrate having a second top surface and a second bottom surface opposite to each other and a second active layer disposed on the second top surface;   bonding the first semiconductor chip to the second semiconductor chip so that the first bottom surface directly contacts the second bottom surface; and   electrically connecting the first semiconductor chip to the second semiconductor chip.   
     
     
         2 . The method of  claim 1 , wherein bonding the first semiconductor chip to the second semiconductor chip includes:
 activating the first bottom surface and the second bottom surface; and   attaching the activated first bottom surface to the activated second bottom surface.   
     
     
         3 . The method of  claim 2 , wherein activating the first bottom surface and the second bottom surface includes irradiating plasma onto the first bottom surface and the second bottom surface. 
     
     
         4 . The method of  claim 2 , wherein activating the first bottom surface and the second bottom surface includes applying ion impact to the first bottom surface and the second bottom surface. 
     
     
         5 . The method of  claim 2 , wherein activating the first bottom surface and the second bottom surface includes irradiating radicals onto the first bottom surface and the second bottom surface. 
     
     
         6 . The method of  claim 1 , wherein electrically connecting the first semiconductor chip to the second semiconductor chip includes forming through electrodes that penetrate the first and second semiconductor chips. 
     
     
         7 . The method of  claim 6 , wherein the through electrodes that penetrate the second semiconductor chips are formed after the attaching process is performed. 
     
     
         8 . The method of  claim 6 , further comprising forming first bumps and second bumps on the first bottom surface and the second bottom surface respectively, after formation of the through electrodes,
 wherein the first bumps are formed to cover first ends of the through electrodes, and the second bumps are formed to cover second ends of the through electrodes.   
     
     
         9 . The method of  claim 7 , after formation of the through electrodes, further comprising:
 forming a redistribution layer on one active layer of the first and second active layers, the redistribution layer being connected to the through electrodes; and   forming bumps on the other active layer of the first and second active layers, the bumps being connected to the through electrodes.   
     
     
         10 . The method of  claim 7 , further comprising:
 forming a redistribution layer on at least one active layer of the first and second active layers, the redistribution layer being connected to the through electrodes; and   forming pads on the redistribution layer.   
     
     
         11 . A method of fabricating a semiconductor package, the method comprising:
 providing a first semiconductor chip including a first substrate having a first top surface and a first bottom surface opposite to each other and a first active layer disposed on the first top surface;   providing a second semiconductor chip including a second substrate having a second top surface and a second bottom surface opposite to each other and a second active layer disposed on the second top surface;   bonding the first semiconductor chip to the second semiconductor chip so that the first bottom surface directly contacts the second bottom surface;   electrically connecting the first semiconductor chip to the second semiconductor chip to form a dual-layered structural semiconductor chip; and   mounting the dual-layered structural semiconductor chip on a substrate.   
     
     
         12 . The method of  claim 11 , further comprising stacking at least one additional dual-layered structural semiconductor chip on the dual-layered structural semiconductor chip. 
     
     
         13 . The method of  claim 11 , wherein bonding the first semiconductor chip to the second semiconductor chip includes:
 activating the first bottom surface and the second bottom surface; and   attaching the activated first bottom surface to the activated second bottom surface.   
     
     
         14 . The method of  claim 13 , wherein activating the first bottom surface and the second bottom surface includes irradiating plasma onto the first bottom surface and the second bottom surface. 
     
     
         15 . The method of  claim 13 , wherein activating the first bottom surface and the second bottom surface includes applying ion impact to the first bottom surface and the second bottom surface. 
     
     
         16 . The method of  claim 13 , wherein activating the first bottom surface and the second bottom surface includes irradiating radicals onto the first bottom surface and the second bottom surface. 
     
     
         17 . The method of  claim 11 , wherein electrically connecting the first semiconductor chip to the second semiconductor chip includes forming through electrodes that penetrate the first and second semiconductor chips. 
     
     
         18 . The method of  claim 17 , wherein the through electrodes that penetrate the second semiconductor chips are formed after the bonding process is performed. 
     
     
         19 . The method of  claim 18 , further comprising forming first bumps and second bumps on the first bottom surface and the second bottom surface respectively, after formation of the through electrodes,
 wherein the first bumps are formed to cover first ends of the through electrodes, and the second bumps are formed to cover second ends of the through electrodes.   
     
     
         20 . The method of  claim 18 , after formation of the through electrodes, further comprising:
 forming a redistribution layer on one active layer of the first and second active layers, the redistribution layer being connected to the through electrodes; and   forming bumps on the other active layer of the first and second active layers, the bumps being connected to the through electrodes.   
     
     
         21 . The method of  claim 18 , further comprising:
 forming a redistribution layer on at least one active layer of the first and second active layers, the redistribution layer being connected to the through electrodes; and   forming pads on the redistribution layer.