Semiconductor device and method of manufacturing same

Abstract

In one embodiment, a semiconductor device includes a substrate, a first inter layer dielectric disposed on the substrate, and a second inter layer dielectric disposed on the first inter layer dielectric. Furthermore, one of the first and second inter layer dielectrics is a first insulator, and the other of the first and second inter layer dielectrics is a second insulator. In addition, the first insulator has a property capable of having a tensile stress in a case where the first insulator is annealed, and the second insulator has a property capable of having a compression stress in a case where the second insulator is annealed.

1 . A semiconductor device comprising:
 a substrate;   a first inter layer dielectric disposed on the substrate; and   a second inter layer dielectric disposed on the first inter layer dielectric,   wherein   one of the first and second inter layer dielectrics is a first insulator,   the other of the first and second inter layer dielectrics is a second insulator,   the first insulator has a property capable of having a tensile stress in a case where the first insulator is annealed, and   the second insulator has a property capable of having a compression stress in a case where the second insulator is annealed.   
     
     
         2 . The device of  claim 1 , wherein the first insulator is a boron phosphorus silicon glass (BPSG) film. 
     
     
         3 . The device of  claim 1 , wherein the second insulator is a tetraethyl orthosilicate (TEOS) film. 
     
     
         4 . The device of  claim 1 , wherein
 the first insulator has a property capable of having the tensile stress in a case where the first insulator is annealed at a predetermined temperature, and   the second insulator has a property capable of having the compression stress in a case where the second insulator is annealed at the predetermined temperature.   
     
     
         5 . The device of  claim 4 , wherein the predetermined temperature is 800° C. or more. 
     
     
         6 . The device of  claim 1 , further comprising a memory disposed on the second inter layer dielectric. 
     
     
         7 . The device of  claim 6 , wherein the memory comprises:
 plural insulating layers and plural electrode layers alternately stacked on the second inter layer dielectric; and   a channel semiconductor layer disposed on side surfaces of the electrode layers via an insulator.   
     
     
         8 . The device of  claim 1 , further comprising a transistor disposed between the substrate and the first inter layer dielectric. 
     
     
         9 . The device of  claim 1 , further comprising one or more inter layer dielectrics disposed between the substrate and the first inter layer dielectric. 
     
     
         10 . The device of  claim 1 , wherein
 a thickness of the second insulator is smaller than a thickness of the first insulator in a case where the compression stress is larger than the tensile stress under assumption that the first and second insulators have the same thickness, and   a thickness of the second insulator is larger than a thickness of the first insulator in a case where the compression stress is smaller than the tensile stress under the assumption that the first and second insulators have the same thickness.   
     
     
         11 . A method of manufacturing a semiconductor device, comprising:
 forming a first inter layer dielectric on a substrate;   forming a second inter layer dielectric on the first inter layer dielectric; and   annealing the first and second inter layer dielectrics,   wherein   one of the first and second inter layer dielectrics is a first insulator,   the other of the first and second inter layer dielectrics is a second insulator,   the first insulator has a tensile stress after the first and second inter layer dielectrics are annealed, and   the second insulator has a compression stress after the first and second inter layer dielectrics are annealed.   
     
     
         12 . The method of  claim 11 , wherein the first insulator is a boron phosphorus silicon glass (BPSG) film. 
     
     
         13 . The method of  claim 11 , wherein the second insulator is a tetraethyl orthosilicate (TEOS) film. 
     
     
         14 . The method of  claim 11 , wherein
 the first insulator has a property capable of having the tensile stress after the first and second inter layer dielectrics are annealed at a predetermined temperature, and   the second insulator has a property capable of having the compression stress after the first and second inter layer dielectrics are annealed at the predetermined temperature.   
     
     
         15 . The method of  claim 14 , wherein the predetermined temperature is 800° C. or more. 
     
     
         16 . The method of  claim 11 , further comprising forming a memory on the second inter layer dielectric. 
     
     
         17 . The method of  claim 16 , wherein the memory comprises:
 plural insulating layers and plural electrode layers alternately stacked on the second inter layer dielectric; and   a channel semiconductor layer formed on side surfaces of the electrode layers via an insulator.   
     
     
         18 . The method of  claim 11 , wherein the first inter layer dielectric is formed on the substrate via a transistor. 
     
     
         19 . The method of  claim 11 , wherein the first inter layer dielectric is formed on the substrate via one or more inter layer dielectrics. 
     
     
         20 . The method of  claim 11 , wherein
 a thickness of the second insulator is set smaller than a thickness of the first insulator in a case where the compression stress is larger than the tensile stress under assumption that the first and second insulators have the same thickness, and   a thickness of the second insulator is set to larger than a thickness of the first insulator in a case where the compression stress is smaller than the tensile stress under the assumption that the first and second insulators have the same thickness.