Physically-addressable solid state disk (ssd) and a method of addressing the same

Abstract

A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD) and is addressable using physical addresses associated with user data that are provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of the user data in the physically-addressed SSD. The flash tables are maintained in the non-volatile memory modules.

What is claimed is: 
     
         1 . A computer system comprising:
 a Central Processing Unit (CPU):   at least one physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, the user data being provided by a host and to be stored in or retrieved from the at least one physically-addressed SSD in blocks;   a non-volatile memory module coupled to the CPU and configured to store changes to flash tables, the flash tables including tables used to map logical to physical blocks for identifying the location of the user data in the at least one physically addressed SSD, wherein the CPU is operable to move the flash tables to the at least one physically-addressable SSDs, the changes to the flash tables being maintained in the non-volatile memory module; and   a network interface controller coupled through a PCIe bus to the CPU.   
     
     
         2 . The computer system, as recited in  claim 1 , wherein the non-volatile memory module includes a cache configured to store the user data. 
     
     
         3 . The computer system, as recited in  claim 1 , wherein the non-volatile memory module being configured to store a journal, the journal being employed to log changes before the non-volatile memory module is updated with the changes. 
     
     
         4 . A computer system comprising:
 a system memory configured to store flash tables and having a bank of volatile RAM modules;   a physically-addressed solid state disk (SSD) addressable using physical addresses associated with user data to be stored in or retrieved from the physically-addressed SSD in blocks, wherein the flash tables including at least one table used to map logical block addresses to physical block addresses, the physical block addresses identifying the location of stored user data in the physically addressed SSD, the physically-addressed SSD configured to store a copy of the flash tables; and   a non-volatile memory module, configured to store changes to the flash tables upon the flash tables being moved to the physically-addressed SSD.   
     
     
         5 . The storage system of  claim 4 , wherein upon the non-volatile memory module reaching a desired available capacity, the flash tables being moved to the system memory. 
     
     
         6 . The storage system, as recited in  claim 4 , wherein the physically-addressed SSD includes a flash subsystem made of flash NAND memory. 
     
     
         7 . The storage system, as recited in  claim 4 , further including a bank of memory controllers coupled to the bank of volatile RAM modules through a respective one of a bank of memory channels. 
     
     
         8 . The storage system of  claim 4 , wherein the bank of memory controllers are a part of a central processing unit (CPU) and wherein the CPU is operable to perform garbage collection on the physically-addressed SSD. 
     
     
         9 . The storage system, as recited in  claim 8 , wherein the at least one physically-addressed SSD is coupled through a PCIe bus to the CPU. 
     
     
         10 . The storage system, as recited in  claim 8 , wherein the at least one physically-addressed SSD is coupled through a flash bus to the CPU. 
     
     
         11 . The storage system, as recited in  claim 4 , wherein the non-volatile memory module includes magnetic random access memory (MRAM). 
     
     
         12 . The storage system, as recited in  claim 4 , wherein the non-volatile memory module includes spin torque transfer magnetic random access memory (STTMRAM). 
     
     
         13 . The storage system, as recited in  claim 4 , wherein the non-volatile memory module is coupled to a CPU through a non-volatile memory channel. 
     
     
         14 . The storage system, as recited in  claim 13 , wherein the non-volatile memory module is coupled to a CPU through a dynamic random access memory (DRAM) memory channel. 
     
     
         15 . The storage system, as recited in  claim 4 , wherein the non-volatile memory module is coupled to a CPU via a system bus. 
     
     
         16 . The storage system, as recited in  claim 4 , wherein the non-volatile memory module is configured to store a cache for caching the user data. 
     
     
         17 . The storage system, as recited in  claim 4 , wherein the non-volatile memory module is configured to store a journal for logging the changes before the changes are committed to the non-volatile memory module. 
     
     
         18 . The storage system, as recited in  claim 4 , further including a CPU coupled to the at least one physically-addressed SSD. 
     
     
         19 . The storage system, as recited in  claim 18 , further including a bridge controller configured to couple the CPU to the at least one physically-addressed SSD. 
     
     
         20 . The storage system, as recited in  claim 19 , wherein the CPU includes a PCIe controller and the bridge controller is coupled to the PCIe controller. 
     
     
         21 . The storage system, as recited in  claim 20 , further including PCIe bus coupled to the CPU and a flash bus coupled to the at least one physically-addressed SSD and wherein the bridge controller is configured to coupled the PCIe bus to the flash bus. 
     
     
         22 . The storage system, as recited in  claim 20 , further including PCIe bus coupled to the CPU and a flash bus coupled to the at least one physically-addressed SSD and wherein the bridge controller is configured to cause coupling between the PCIe bus and the flash bus.