Memory system provided with nand flash memory and method including simultaneously writing data to first and second districts

Abstract

A memory system includes first and second districts, and a control section. Each of the first and second districts includes a memory cell array. The control section receives a single write command to simultaneously write first data to the first and second districts. A memory controller may subsequently issue a read command to read the first data from one of the memory cell arrays to determine whether the read first data is normal or is correctable based on a result of error correction in an error correction circuit. When the read first data is normal, the first data written to the other of the memory cell arrays may be deleted or nullified.

1 - 13 . (canceled) 
     
     
         14 . A memory system comprising:
 a flash memory including first and second districts; and   a memory controller including an error correction circuit, wherein   the memory controller is configured to issue a write command to the flash memory to simultaneously write first data to both of the first and second districts, issue a read command to the flash memory to read the first data from one of the first and second districts, and determine whether or not the first data read from the one of the first and second districts is correctable based on a result of error correction in the error correction circuit, and   the memory controller is configured to perform issuing the write command, and each of issuing the read command and determining whether or not the first data is correctable when executing a data write in reply to the write command.   
     
     
         15 . The system of  claim 14 , wherein when the first data read from the one of the first and second districts is correctable, the memory controller is configured to instruct the internal controller to delete the first data written to the other of the first and second districts. 
     
     
         16 . The system of  claim 14 , wherein upon receipt of a read instruction from the external host device, the memory controller is configured to determine whether or not the first data has been written to the first and second districts on the basis of a history of write to the first and second districts and, when the first data has been written to the first and second districts, reads the first data from one of the first and second districts. 
     
     
         17 . The system of  claim 14 , wherein
 the first district comprises:
 a first memory cell array including a plurality of memory cells; 
 a first row decoder configured to select one of the plurality of memory cells of the first memory cell array; and 
 a first sense amplifier configured to detect data read from the first memory cell array; and 
   the second district comprises:
 a second memory cell array including a plurality of memory cells; 
 a second row decoder configured to select one of the plurality of memory cells of the second memory cell array; and 
 a second sense amplifier configured to detect data read from the second memory cell array. 
   
     
     
         18 . The system of  claim 14 , wherein the internal controller includes an address decoder configured to receive first and second addresses, supply the first address to the first district, and supply the second address to the second district. 
     
     
         19 . A memory system comprising:
 a flash memory including first and second districts; and   a memory controller including an error correction circuit, wherein   the memory controller writes first data to both of the first and second districts, and   the memory controller, after writing the first data, reads the first data from one of the first and second districts and determines the first data read from the one of the first and second districts is correctable based on a result of error correction in the error correction circuit.