Data Alignment over Multiple Physical Lanes

Abstract

High speed communication networks divide data traffic into multiple physical lanes. For example, the IEEE standard 40G/100G supports sending Ethernet frames at 40/100 gigabits per second over multiple 10/25 Gb/s lanes. Techniques are disclosed for aligning the data across the physical lanes.

1 .- 20 . (canceled) 
     
     
         21 . A method comprising:
 receiving multiple alignment markers for a first communication lane, the multiple alignment markers organized into a first group with a predetermined number of alignment markers;   determining to check a first alignment marker of the multiple alignment markers, the first alignment marker assigned to the first group;   checking the first alignment marker by:
 determining a number of symbol errors in the first alignment marker; and 
 comparing the number of symbol errors in first alignment marker to a lock threshold; and 
   responsive to determining to check the first alignment marker of the first group, forgoing a check of a second alignment marker of the multiple alignment markers, the second alignment marker also assigned to the first group.   
     
     
         22 . The method of  claim 21  further comprising determining to lock when the number of symbol errors meets the lock threshold. 
     
     
         23 . The method of  claim 22 , further comprising determining to check a third alignment marker for the first communication lane after checking the first alignment marker. 
     
     
         24 . The method of  claim 23 , where the first, second, and third alignment markers comprise consecutive alignment markers within the first group. 
     
     
         25 . The method of  claim 23 , where the first and third alignment markers comprise non-consecutive alignment markers. 
     
     
         26 . The method of  claim 23 , where the third alignment marker is assigned to a second group, the second group different from the first group. 
     
     
         27 . The method of  claim 21 , where the first group is received within a forward error correction (FEC) block for the first communication lane. 
     
     
         28 . The method of  claim 21  where determining the number of symbol errors in first alignment marker comprises analyzing symbols in first alignment marker against a predefined data pattern. 
     
     
         29 . The method of  claim 28 , where the predefined data pattern comprises a virtual lane marker pattern. 
     
     
         30 . The method of  claim 28 , where comparing the number of symbol errors in the data to the lock threshold comprises:
 tolerating a pre-defined number of the symbol errors in determining that there is a match to the predefined data pattern.   
     
     
         31 . The method of  claim 21 , further comprising:
 determining to lock responsive to matching a pre-defined number of consecutive data patterns; and   reading alignment parameters that specify the pre-defined number of consecutive data patterns.   
     
     
         32 . The method of  claim 21 , further comprising checking a third alignment marker of the multiple alignment markers that distinguishes the communication lane from other communication lanes to identify the communication lane. 
     
     
         33 . A device comprising:
 a communication interface configured to multiple alignment markers for a first communication lane, the multiple alignment markers included within first error correction block with a pre-determined of alignment markers; and   circuitry in communication with the communication interface, the circuitry configured to:
 determine a first number of symbol errors for a first alignment marker of the multiple alignment markers, the first alignment marker included within the first error correction block; 
 determine a second number of symbol errors for a second alignment marker of the multiple alignment markers, the second alignment marker also included within the first error correction block; 
 compare the first number of symbol errors to a lock threshold; 
 compare the second number of symbol errors to the lock threshold; and 
 lock on the first communication lane when the first number of symbol errors is below the lock threshold and the second number of symbol errors is below the lock threshold. 
   
     
     
         34 . The device of  claim 33 , where the circuitry is further configured to check a third alignment marker for the first communication lane before locking on the first communication lane. 
     
     
         35 . The device of  claim 34 , where the first, second, and third alignment markers comprise consecutive alignment markers within the first error correction block. 
     
     
         36 . The device of  claim 34 , where the third alignment marker is included within a second error correction block, the second error correction block different from the first error correction block. 
     
     
         37 . The device of  claim 33 , where the first and second alignment markers comprise non-consecutive alignment markers within the first error correction block. 
     
     
         38 . A device comprising:
 a communication interface configured to multiple alignment markers for a first communication lane, the multiple alignment markers included within a first group with a pre-determined of alignment markers; and   circuitry in communication with the communication interface, the circuitry configured to:
 determine to check a first alignment marker of the multiple alignment markers, the first alignment marker assigned to the first group; 
 checking the first alignment marker by:
 determining a number of symbol errors in the first alignment marker; and 
 comparing the number of symbol errors in first alignment marker to a lock threshold; and 
 
 responsive to determining to check the first alignment marker of the first group, forgo a check of a second alignment marker of the multiple alignment markers, the second alignment marker also assigned to the first group. 
   
     
     
         39 . The device of  claim 38 , where the circuitry is further configured to determine to remain out-of-lock when the number of symbol errors is below the lock threshold. 
     
     
         40 . The device of  claim 38 , where the circuitry is further configured to:
 determine the number of symbol errors for the first alignment marker by analyzing symbols in first alignment marker against a predefined data pattern; and   compare the number of symbol errors in the data to the lock threshold comprises by tolerating a pre-defined number of the symbol errors in declaring a match to the predefined data pattern.