Semiconductor device

Abstract

A gate interconnection portion (GHB) includes a first gate interconnection portion (GHB 1 ), a second gate interconnection portion (GHB 2 ), and a third gate interconnection portion (GHB 3 ). The first gate interconnection portion (GHB 1 ) is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region (PER). The second gate interconnection portion (GHB 2 ) is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion (GHB 1 ) toward the power supply interconnection, and extends across a boundary between the element formation region (PER) and an element isolation insulating film (EB), which is in parallel to an X axis direction. The third gate interconnection portion (GHB 3 ) further extends in parallel to the Y-axis direction from the second gate interconnection portion (GHB 2 ) toward the power supply interconnection.

1 - 7 . (canceled) 
     
     
         8 . A semiconductor device including an inverter circuit in which complementary switching elements are connected in series between a power supply potential and a ground potential, comprising:
 a semiconductor substrate having a main surface;   a power supply interconnection formed on a surface of said semiconductor substrate and extending in parallel to a first direction, to which a power supply potential is applied;   a ground interconnection formed on the surface of said semiconductor substrate and extending in parallel to said first direction at a distance from said power supply interconnection in a second direction orthogonal to said first direction, to which a ground potential is applied; and   two element formation regions for said complementary switching elements, each defined by an element isolation insulating film in a region of said semiconductor substrate lying between said power supply interconnection and said ground interconnection,   each said element formation region having formed
 a gate interconnection portion intersecting said element formation region, 
 a source and a drain, 
 a tap region electrically connected to a corresponding interconnection of said power supply interconnection and said ground interconnection, and 
 a metal silicide film covering butting diffusion of said tap region and one of said source and said drain, 
   said gate interconnection portion including
 a first gate interconnection portion formed in parallel to said second direction and extending toward a side where the corresponding interconnection is arranged to a prescribed position within said element formation region, and 
 a second gate interconnection portion extending obliquely from said first gate interconnection portion toward said side where the corresponding interconnection is arranged, and extending obliquely across a boundary parallel to said first direction which is a boundary between said element formation region and said element isolation insulating film. 
   
     
     
         9 . The semiconductor device according to  claim 8 , wherein
 said gate interconnection portion includes a third gate interconnection portion extending in parallel to said second direction from said second gate interconnection portion.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein
 said second gate interconnection portion extends over said element isolation insulating film.   
     
     
         11 . The semiconductor device according to  claim 8 , wherein
 an angle formed by said second gate interconnection portion with respect to said first gate interconnection portion is from 10° to 80°.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein
 an angle formed by said second gate interconnection portion with respect to said first gate interconnection portion is 45°.   
     
     
         13 . The semiconductor device according to  claim 11 , wherein
 said gate interconnection portion includes a gate interconnection main body having opposing sides opposed at a distance from each other, and   said gate interconnection main body has a terminal end orthogonal to said opposing sides.   
     
     
         14 . A semiconductor device, comprising:
 a semiconductor substrate having a main surface; and   an element formation region defined by an element isolation insulating film in said semiconductor substrate,   said element formation region having formed
 a gate interconnection portion intersecting said element formation region, 
 a source and a drain, 
 a tap region to which a prescribed potential is applied, and 
 a metal silicide film covering butting diffusion of said tap region and one of said source and said drain, 
   said gate interconnection portion including
 a first gate interconnection portion formed in a direction orthogonal to a direction in which a boundary between said element formation region and said element isolation insulating film extends, toward said boundary, and extending to a prescribed position within said element formation region, and 
 a second gate interconnection portion bending from said first gate interconnection portion and extending obliquely across said boundary.