Nonvolatile semiconductor memory device having element isolating region of trench type

Abstract

Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

1 - 19 . (canceled) 
     
     
         20 . A semiconductor device comprising:
 a semiconductor layer;   a memory transistor; and   a peripheral circuit transistor;   wherein the memory transistor comprises:
 a first insulating film formed on the semiconductor layer in a memory cell region; 
 a first electrode layer formed on the first insulating film; 
 a first element isolating insulator formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, a top face of the first element isolating insulator being lower than a top face of the first electrode layer; 
 a second insulating film formed on the first electrode layer and the first element isolating insulator; 
 a second electrode layer formed on the second insulating film; and 
   the peripheral circuit transistor comprises:
 a third insulating film formed on the semiconductor layer in a peripheral circuit region; 
 a third electrode layer formed on the third insulating film; 
 a second element isolating insulator formed to extend through the third electrode layer and the third insulating film to reach an inner region of the semiconductor layer; 
 a fourth insulating film formed on the third electrode layer, the fourth insulating film including a first open portion exposing a surface of the third electrode layer; 
 a fourth electrode layer formed on the fourth insulating film and electrically connecting to the third electrode layer through the first open portion; 
 a fifth insulating film formed above the fourth electrode; 
 a contact hole extending through the fifth insulating film; and 
 a contact formed in the contact hole to electrically connect to the fourth electrode layer, and the contact arranged above the third electrode layer and the fourth insulating film. 
   
     
     
         21 . The semiconductor device according to  claim 20 , wherein the first open portion and the contact are arranged in a gate width direction of the peripheral circuit transistor. 
     
     
         22 . The semiconductor device according to  claim 20 , wherein a width of the first open portion is longer than a width of the contact in a gate width direction of the peripheral circuit transistor. 
     
     
         23 . The semiconductor device according to  claim 20 , wherein the contact includes a barrier metal film including Ti. 
     
     
         24 . The semiconductor device according to  claim 20 , wherein the fourth insulating film is a complex insulating film including a silicon nitride film. 
     
     
         25 . The semiconductor device according to  claim 20 , wherein the fourth insulating film presents at an end portion of the fourth electrode layer. 
     
     
         26 . The semiconductor device according to  claim 20 , wherein a stack of the fourth insulating film and the fourth electrode layer extends from the third electrode layer to the second element isolating insulator. 
     
     
         27 . The semiconductor device according to  claim 20 , wherein a thickness of the first element isolating insulator is thinner than a thickness of the second element isolating insulator. 
     
     
         28 . The semiconductor device according to  claim 20 , wherein a thickness of the first insulating film is substantially same as a thickness of the third insulating film. 
     
     
         29 . A semiconductor device comprising:
 a semiconductor layer;   a memory transistor; and   a first peripheral circuit transistor;   wherein the memory transistor comprises:
 a first insulating film formed on the semiconductor layer in a memory cell region; 
 a first electrode layer formed on the first insulating film; 
 a first element isolating insulator formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, a top face of the first element isolating insulator being lower than a top face of the first electrode layer; 
 a second insulating film formed on the first electrode layer and the first element isolating insulator; 
 a second electrode layer formed on the second insulating film; 
 a third insulating film formed above the second electrode; 
 a first contact hole extending through the third insulating film; 
 a first contact formed in the contact hole to electrically connect to the second electrode layer; and 
 a first wiring electrically connected to the second electrode layer via the first contact; and 
   the first peripheral circuit transistor comprises:
 a fourth insulating film formed on the semiconductor layer in a peripheral circuit region; 
 a third electrode layer formed on the fourth insulating film; 
 a second element isolating insulator formed to extend through the third electrode layer and the fourth insulating film to reach an inner region of the semiconductor layer; 
 a fifth insulating film formed on the third electrode layer, the fifth insulating film including a first open portion exposing a surface of the third electrode layer; 
 a fourth electrode layer formed on the fifth insulating film and electrically connecting to the third electrode layer through the first open portion; 
 a sixth insulating film formed above the fourth electrode; 
 a second contact hole extending through the sixth insulating film; and 
 a second contact formed in the contact hole to electrically connect to the fourth electrode layer, and the second contact arranged above the third electrode layer and the fifth insulating film; and 
 a second wiring electrically connected to the fourth electrode layer via the second contact. 
   
     
     
         30 . The semiconductor device according to  claim 29 , wherein the first wiring and the second wiring are arranged in a same wiring layer. 
     
     
         31 . The semiconductor device according to  claim 29 , further comprising a second peripheral circuit transistor,
 the second peripheral circuit transistor comprises:
 a seventh insulating film formed on the semiconductor layer in the peripheral circuit region; 
 a fifth electrode layer formed on the seventh insulating film; 
 a third element isolating insulator formed to extend through the fifth electrode layer and the seventh insulating film to reach an inner region of the semiconductor layer; 
 an eighth insulating film formed on the fifth electrode layer, the eighth insulating film including a third open portion exposing a surface of the fifth electrode layer; 
 a sixth electrode layer formed on the eighth insulating film and electrically connecting to the fifth electrode layer through the third open portion; 
 a ninth insulating film formed above the sixth electrode; 
 a third contact hole extending through the ninth insulating film; and 
 a third contact formed in the third contact hole to electrically connect to the sixth electrode layer. 
   
     
     
         32 . The semiconductor device according to  claim 29 , wherein the first peripheral circuit transistor is adjacent to the second peripheral circuit transistor in a gate width direction, and the third contact arranged above the fifth electrode layer and the eighth insulating film. 
     
     
         33 . The semiconductor device according to  claim 29 , wherein the third contact is arranged above the third element isolating insulator. 
     
     
         34 . The semiconductor device according to  claim 29 , wherein the first open portion and the second contact are arranged in a gate width direction of the first peripheral circuit transistor. 
     
     
         35 . The semiconductor device according to  claim 29 , wherein a width of the first open portion is longer than a width of the second contact in a gate width direction of the first peripheral circuit transistor. 
     
     
         36 . The semiconductor device according to  claim 29 , wherein the second contact includes a barrier metal film including Ti. 
     
     
         37 . The semiconductor device according to  claim 29 , wherein the fifth insulating film is a complex insulating film including a silicon nitride film. 
     
     
         38 . The semiconductor device according to  claim 29 , wherein the fifth insulating film presents at an end portion of the fourth electrode layer. 
     
     
         39 . The semiconductor device according to  claim 29 , wherein a stack of the fifth insulating film and the fourth electrode layer extends from the third electrode layer to the second element isolating insulator.