Multilayer ceramic capacitor and board having the same

Abstract

A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes three external electrodes including a conductive layer, a nickel plating layer, and a tin plating layer sequentially stacked on a mounting surface of the ceramic body, and spaced apart from each other. When an outermost portion of a lead-out portion of an internal electrode exposed to the mounting surface is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is b p , (b−b p )/a satisfies 0.264≦(b−b p )/a≦0.638.

What is claimed is: 
     
         1 . A multilayer ceramic capacitor comprising:
 a ceramic body including a plurality of dielectric layers stacked therein;   a plurality of first and second internal electrodes alternately disposed in the ceramic body, each first and second internal electrodes interposed between the respective dielectric layer, and the first and second internal electrodes including first and second body portions overlapped with each other and first and second lead-out portions extended from the first and second body portions to be exposed to one surface of the ceramic body, respectively; and   first and second external electrodes formed on the one surface of the ceramic body to be connected to the first and second lead-out portions, respectively,   wherein in the first and second external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the one surface of the ceramic body, and   when an outermost portion of one of the first and second lead-out portions exposed to the one surface of the ceramic body is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is b p , (b−b p )/a satisfies 0.264≦(b−b p )/a≦0.638.   
     
     
         2 . The multilayer ceramic capacitor of  claim 1 , wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is c, b/c satisfies 0.930≦b/c≦5.391. 
     
     
         3 . A multilayer ceramic capacitor comprising:
 a ceramic body including a plurality of dielectric layers stacked in a width direction of the ceramic body;   an active layer including a plurality of first and second internal electrodes alternately disposed in the ceramic body to have a respective dielectric layer interposed between the first and second internal electrodes;   first and second lead-out portions extended from the first internal electrode to be exposed to a mounting surface of the ceramic body, and spaced apart from each other in a length direction of the ceramic body;   a third lead-out portion extended from the second internal electrode to be exposed to the mounting surface of the ceramic body, and disposed between the first and second lead-out portions;   first and second external electrodes disposed on the mounting surface of the ceramic body to be spaced apart from each other in the length direction, and connected to the first and second lead-out portions, respectively; and   a third external electrode formed on the mounting surface of the ceramic body to be located between the first and second external electrodes, and connected to the third lead-out portion,   wherein in the first to third external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the mounting surface of the ceramic body, and   when an outermost portion of one of the first to third lead-out portions exposed to the mounting surface of the ceramic body is defined as P, a total thickness of the conductive layer, the nickel plating layer, and the tinplating layer in a normal line direction of the conductive layer from P is defined as a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is defined as b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is defined as b p , (b−b p )/a satisfies 0.264≦(b−b p )/a≦0.638.   
     
     
         4 . The multilayer ceramic capacitor of  claim 3 , wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is c, b/c satisfies 0.930≦b/c≦5.391. 
     
     
         5 . The multilayer ceramic capacitor of  claim 3 , wherein the first and second internal electrodes are disposed to be spaced apart from both end surfaces of the ceramic body in the length direction. 
     
     
         6 . The multilayer ceramic capacitor of  claim 3 , wherein the first to third external electrodes are extended to portions of both side surfaces of the ceramic body in the width direction, respectively. 
     
     
         7 . The multilayer ceramic capacitor of  claim 3 , further comprising:
 fourth and fifth lead-out portions extended from the first internal electrode to be exposed to a surface opposing the mounting surface of the ceramic body, and disposed to be spaced apart from each other in the length direction of the ceramic body;   a sixth lead-out portion extended from the second internal electrode to be exposed to the surface opposing the mounting surface of the ceramic body, and disposed between the fourth and fifth lead-out portions; and   an insulating layer disposed on the surface opposing the mounting surface of the ceramic body.   
     
     
         8 . The multilayer ceramic capacitor of  claim 3 , wherein the first internal electrode has fourth and fifth lead-out portions spaced apart from each other in the length direction and exposed to the surface opposing the mounting surface of the ceramic body, and
 the second internal electrode has a sixth lead-out portion exposed to the surface opposing the mounting surface of the ceramic body, and formed between the fourth and fifth lead-out portions to be spaced apart from the fourth and fifth lead-out portions,   the multilayer ceramic capacitor further comprising:   fourth and fifth external electrodes formed on the surface opposing the mounting surface of the ceramic body to be spaced apart from each other in the length direction and connected to the fourth and fifth lead-out portions, respectively; and   a sixth external electrode formed on the surface opposing the mounting surface of the ceramic body to be spaced apart from the respective fourth and fifth external electrodes and connected to the sixth lead-out portion.   
     
     
         9 . The multilayer ceramic capacitor of  claim 8 , wherein in the fourth to sixth external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the surface opposing the mounting surface of the ceramic body, and
 when an outermost portion of one of the fourth to sixth lead-out portions exposed to the surface opposing the mounting surface of the ceramic body is defined as P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is defined as a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is defined as b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is defined as b p , (b−b p )/a satisfies 0.264≦(b−b p )/a≦0.638.   
     
     
         10 . The multilayer ceramic capacitor of  claim 9 , wherein in the fourth to sixth external electrodes, when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is defined as c, b/c satisfies 0.930≦b/c≦5.391. 
     
     
         11 . The multilayer ceramic capacitor of  claim 8 , wherein the fourth to sixth external electrodes are extended to portions of both side surfaces of the ceramic body in the width direction. 
     
     
         12 . The multilayer ceramic capacitor of  claim 3 , further comprising cover layers formed on both sides of the active layer in the width direction. 
     
     
         13 . A multilayer ceramic capacitor comprising:
 a ceramic body including a plurality of dielectric layers stacked in a width direction and having first and second main surfaces opposing each other in a thickness direction of the ceramic body, first and second side surfaces opposing each other in the width direction of the ceramic body, and first and second end surfaces opposing each other in a length direction of the ceramic body;   an active layer including a plurality of first and second internal electrodes alternately disposed in the ceramic body, each first and second internal electrodes interposed between the respective dielectric layer, the first internal electrode including first and second lead-out portions spaced apart from each other in the length direction and exposed to the first main surface of the ceramic body, the first internal electrode being spaced apart from the first and second end surfaces, and the second internal electrode including third and fourth lead-out portions exposed to the first main surface of the ceramic body and disposed alternately with the first and second lead-out portions, the second internal electrode being spaced apart from the first and second end surfaces;   cover layers disposed on both sides of the active layer;   first and second external electrodes formed on the first main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the first and second lead-out portions, respectively; and   third and fourth external electrodes formed on the first main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the third and fourth lead-out portions, respectively,   wherein in the first to fourth external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the first main surface of the ceramic body, and   when an outermost portion of one of the first to fourth lead-out portions exposed to the first main surface of the ceramic body is P, a total thickness of the conductive layer, the nickel plating layer, and the tinplating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is b p , (b−b p )/a satisfies 0.264≦(b−b p )/a≦0.638.   
     
     
         14 . The multilayer ceramic capacitor of  claim 13 , wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is defined as c, b/c satisfies 0.930≦b/c≦5.391. 
     
     
         15 . The multilayer ceramic capacitor of  claim 13 , wherein the first internal electrode has fifth and sixth lead-out portions spaced apart from each other in the length direction and exposed to the second main surface of the ceramic body, and
 the second internal electrode has seventh and eighth lead-out portions exposed to the second main surface of the ceramic body and formed alternately with the fifth and sixth lead-out portions, and   the multilayer ceramic capacitor further comprising:   fifth and sixth external electrodes formed on the second main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the fifth and sixth lead-out portions, respectively; and   seventh and eighth external electrodes formed on the second main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the seventh and eighth lead-out portions, respectively.   
     
     
         16 . The multilayer ceramic capacitor of  claim 15 , wherein in the fifth to eighth external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the second main surface of the ceramic body, and
 when an outermost portion of one of the fifth to eighth lead-out portions exposed to the second main surface of the ceramic body is defined as P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is defined as a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is defined as b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is defined as b p , (b−b p )/a satisfies 0.264≦(b−b p )/a≦0.638.   
     
     
         17 . The multilayer ceramic capacitor of  claim 16 , wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is defined as c, b/c satisfies 0.930≦b/c≦5.391. 
     
     
         18 . A board including a multilayer ceramic capacitor comprising:
 a substrate including a plurality of electrode pads formed on the substrate; and   the multilayer ceramic capacitor of  claim 1 , mounted on the electrode pads of the substrate.   
     
     
         19 . A board including a multilayer ceramic capacitor comprising:
 a substrate including a plurality of electrode pads formed on the substrate; and   the multilayer ceramic capacitor of  claim 3 , mounted on the electrode pads of the substrate.   
     
     
         20 . A board including a multilayer ceramic capacitor comprising:
 a substrate including a plurality of electrode pads formed on the substrate; and   the multilayer ceramic capacitor of  claim 13 , mounted on the electrode pads of the substrate.