Methods for controlling the use of intellectual property in individual integrated circuit devices

Abstract

A method for controlling the use of intellectual property (IP) in an individual integrated circuit includes loading data including the IP into the individual integrated circuit, loading an IP license certificate into the individual integrated circuit, the certificate including identification of the IP authorized for the individual integrated circuit, determining inside the individual integrated circuit whether the IP is authorized for the individual integrated circuit, enabling operation of the individual integrated circuit if the IP circuit is authorized for use in the individual integrated circuit, and imposing a penalty on operation of the individual integrated circuit if the IP is not authorized for use in the individual integrated circuit.

What is claimed is: 
     
         1 . A method for controlling the use of intellectual property (IP) in an individual integrated circuit, comprising:
 loading data including the IP into the individual integrated circuit;   loading information into the individual integrated circuit, the information including identification of the IP authorized for the individual integrated circuit;   determining inside the individual integrated circuit whether the loaded IP is authorized for the individual integrated circuit;   enabling operation of the individual integrated circuit if the loaded IP is authorized for use in the individual integrated circuit; and   imposing a penalty on operation of the individual integrated circuit if the loaded IP is not authorized for use in the individual integrated circuit.   
     
     
         2 . The method of  claim 1 , wherein the integrated circuit is a field programmable gate array (FPGA) and:
 loading data including the IP into the individual integrated circuit comprises loading data including the IP into the individual FPGA;   loading information into the individual integrated circuit, the information including identification of the IP authorized for the individual integrated circuit comprises loading the information into the individual FPGA, the information including identification of the IP authorized for the individual FPGA;   determining inside the individual integrated circuit whether the loaded IP is authorized for the individual integrated circuit comprises determining inside the individual FPGA whether the loaded IP is authorized for the individual FPGA;   enabling operation of the individual integrated circuit if the loaded IP is authorized for use in the individual integrated circuit comprises enabling operation of the individual FPGA if the loaded IP is authorized for use in the individual FPGA; and   imposing a penalty on operation of the individual integrated circuit if the loaded IP is not authorized for use in the individual integrated circuit comprises imposing a penalty on operation of the individual FPGA if the loaded IP is not authorized for use in the individual FPGA.   
     
     
         3 . The method of  claim 2 , further comprising:
 providing at least one level of optional functionality in the individual FPGA;   determining inside the individual FPGA whether the at least one level of functionality has been authorized for use in the individual FPGA; and   enabling the at least one level of optional functionality in the individual FPGA only if it has been determined inside the individual FPGA that the at least one level of functionality has been authorized for use in the individual FPGA.   
     
     
         4 . The method of  claim 3 , wherein:
 providing at least one level of optional functionality in the individual FPGA comprises providing selectable levels of functionality in the individual FPGA;   determining inside the individual FPGA whether the at least one level of functionality has been authorized for the individual FPGA comprises determining which of the selectable levels of functionality in the individual FPGA have been authorized; and   enabling the at least one level of optional functionality in the individual FPGA comprises enabling the selectable levels of functionality in the individual FPGA that have been authorized.   
     
     
         5 . The method of  claim 4 , wherein providing selectable levels of functionality in the individual FPGA comprises providing that the optional functionality does not operate, providing that the optional functionality does operate, and providing that the optional functionality operates for a limited period of time. 
     
     
         6 . The method of  claim 5 , wherein providing that the optional functionality operates for a limited period of time comprises providing that the optional functionality operates for a limited period of time only if it is determined in the FPGA that the optional functionality operates for a limited period of time. 2R30575.DOCX Page 27 of 30 
     
     
         7 . The method of  claim 2 , wherein imposing a penalty on operation of the individual FPGA if the at least one controlled IP circuit block is not authorized for use in the individual FPGA comprises disabling at least one clock circuit in the individual FPGA. 
     
     
         8 . The method of  claim 2 , wherein imposing a penalty on operation of the individual FPGA if the at least one controlled IP circuit block is not authorized for use in the individual FPGA comprises disabling at least one input/output circuit in the individual FPGA. 
     
     
         9 . The method of  claim 2 , wherein:
 loading information into the individual integrated circuit comprises loading an IP license certificate into the individual FPGA, the certificate including a list of controlled IP circuit blocks authorized for the individual FPGA; and   wherein determining inside the individual FPGA whether the at least one controlled IP circuit block is authorized for use in the individual FPGA comprises comparing the at least one controlled IP circuit block in the design file loaded into the individual FPGA with the list of controlled IP circuit blocks authorized for the individual FPGA contained in the IP license certificate.   
     
     
         10 . A method for controlling the use of intellectual property (IP) in an individual field programmable gate array (FPGA), comprising:
 loading a design file into the individual FPGA, the design file including at least one controlled IP circuit block;   determining inside the individual FPGA whether the at least one controlled IP circuit block is authorized for use in the individual FPGA;   enabling operation of the at least one controlled IP circuit block if the at least one controlled IP circuit block is authorized for use in the individual FPGA; and   imposing a penalty on operation of the individual FPGA if the at least one controlled IP circuit block is not authorized for use in the individual FPGA. 2R30575.DOCX Page 28 of 30   
     
     
         11 . The method of  claim 10 , wherein determining inside the individual FPGA whether the at least one controlled IP circuit block is authorized for use in the individual FPGA comprises:
 loading information into the individual FPGA, the information including a list of controlled IP circuit blocks authorized for the individual FPGA; and   comparing the at least one controlled IP circuit block in the design file loaded into the individual FPGA with the list of controlled IP circuit blocks authorized for the individual FPGA contained in the information.   
     
     
         12 . The method of  claim 11 , wherein:
 loading information into the individual integrated circuit comprises loading an IP license certificate into the individual FPGA, the certificate including a list of controlled IP circuit blocks authorized for the individual FPGA; and   wherein determining inside the individual FPGA whether the at least one controlled IP circuit block is authorized for use in the individual FPGA comprises comparing the at least one controlled IP circuit block in the design file loaded into the individual FPGA with the list of controlled IP circuit blocks authorized for the individual FPGA contained in the IP license certificate.   
     
     
         13 . The method of  claim 1 , wherein:
 data including the IP comprises the IP and data including metadata associated with the IP;   the information including identification of the IP authorized for the individual integrated circuit comprises information identifying the IP authorized for the individual integrated circuit and information including additional rule-related data;   determining inside the individual integrated circuit whether the loaded IP is authorized for the individual integrated circuit comprises determining inside the individual integrated circuit whether the loaded IP is included in the information identifying the IP authorized for the individual integrated circuit and determining inside the individual integrated circuit whether all additional rules defined by the metadata associated with the IP together with the additional rule-related data have been met; and 2R30575.DOCX Page 29 of 30   imposing a penalty on operation of the individual integrated circuit if the loaded IP is not authorized for use in the individual integrated circuit comprises imposing a penalty on operation of the individual integrated circuit if any of the loaded IP is not identified by the information identifying the IP authorized for the individual integrated circuit or any of the rules specified by the metadata associated with the IP together with the additional rule-related data have not been met.   
     
     
         14 . An individual integrated circuit comprising:
 an IP enforcer circuit operable to compare IP that has been downloaded into the individual integrated circuit to a list of controlled IP that is authorized for use in the individual integrated circuit; and   a penalty circuit coupled to the IP enforcer circuit and configured to allow the integrated circuit to be fully operable if all of the IP that has been downloaded into the individual integrated circuit is authorized for use in the individual integrated circuit and to disable at least a portion of the functioning of the integrated circuit if any of IP that has been downloaded into the individual integrated circuit is not authorized for use in the individual integrated circuit.   
     
     
         15 . The individual integrated circuit of  claim 14 , wherein the list of controlled IP that is authorized for use in the individual integrated circuit is stored in a memory on the individual integrated circuit.