Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.

What is claimed is: 
     
         1 . A semiconductor device comprising a p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. 
     
     
         2 . The device according to  claim 1 , wherein the copper monoxide is expressed by the formula (OCu 2 ) x +(Cu 1-2 ) y ,
 wherein x and y satisfy inequalities 0.05≦x<1 and 0.01≦y≦0.9, respectively.   
     
     
         3 . The device according to  claim 1 , wherein the tin monoxide is expressed by the formula (OSn) z +(Sn 1-2 ) w ,
 wherein z and w satisfy inequalities 0.05≦z<1 and 0.01≦w≦0.9, respectively.   
     
     
         4 . The device according to  claim 1 , wherein the copper tin oxide is expressed by the formula (O—Cu—Sn) a +(Cu α —Sn β ) b ,
 wherein α and β satisfy inequalities 0<α<2 and 0<β<2, respectively, and a and b satisfy inequalities 0.05≦a<1 and 0.01≦b≦0.9, respectively. 
 
     
     
         5 . The device according to  claim 1 , wherein the nickel tin oxide is expressed by the formula (O—Ni) a +(Ni α —Sn β ) b ,
 wherein α and β satisfy inequalities 0<α<2 and 0<β<2, respectively, and a and b satisfy inequalities 0.05≦a<1 and 0.01≦b≦0.9, respectively. 
 
     
     
         6 . The device according to  claim 1 , wherein the p-type oxide layer has an amorphous structure, a nano-crystalline structure, or a polycrystalline structure. 
     
     
         7 . The device according to  claim 1 , further comprising a substrate formed of glass, a metal, silicon, a polymer, and cellulose paper. 
     
     
         8 . The device according to  claim 1 , wherein the p-type oxide layer is formed of impurities of 0.2% by weight, based on a total weight thereof to control hole carriers. 
     
     
         9 . The device of  claim 1 , wherein the p-type oxide layer has nonconductor, conductor, or semiconductor characteristics according to oxygen(O) content. 
     
     
         10 . The device of  claim 1 , further comprising a protective layer disposed on the p-type oxide layer and formed of magnesium fluoride (MgF 2 ), silicon oxide (SiO 2 ), or silicon nitride (Si 3 N 4 ). 
     
     
         11 . The device of  claim 1 , further comprising:
 an insulating layer disposed on or under the p-type oxide layer; and   a matching layer interposed between the insulating layer and the p-type oxide layer and formed of tantalum pentoxide.   
     
     
         12 . The device of  claim 1 , wherein the semiconductor device is a complementary metal-oxide-semiconductor (CMOS) device, a thin-film transistor (TFT), a heterojunction device, a logic gate, a PN junction device, a metal-insulator-semiconductor junction device, a light-emitting diode (LED) device, or an optical sensor,
 wherein the p-type oxide layer is a channel layer, a gate electrode, a source electrode, a drain electrode, or a semiconductor layer of the semiconductor device.   
     
     
         13 . The device of  claim 1 , wherein the semiconductor device is a p-type field-effect transistor (FET), and the p-type oxide layer is a channel layer of the p-type FET, the device further comprising:
 a gate electrode disposed on a substrate;   a gate insulating layer disposed on the gate electrode;   a matching layer interposed between the gate insulating layer and the channel layer; and   source and drain electrodes configured to contact both ends of the channel layer.   
     
     
         14 . The device of  claim 13 , wherein the channel layer has a thickness between 0.5 and 100000 nm. 
     
     
         15 . The device of  claim 1 , wherein the semiconductor device is a p-n junction device, and the p-type oxide layer is a p-type semiconductor layer of the p-n junction device, the device further comprising:
 an n-type semiconductor layer disposed on a substrate; and   a matching layer interposed between the n-type semiconductor layer and the p-type semiconductor layer.   
     
     
         16 . The device of  claim 15 , wherein the p-type semiconductor layer has a thickness between 5 and 100000 nm. 
     
     
         17 . The device of  claim 1 , wherein when the p-type oxide layer has an electrical conductivity of about 10 −6  S/cm −1  or lower, the p-type oxide layer is used as a blocking layer configured to block electrons or holes.