Semiconductor device manufacturing method and semiconductor device

Abstract

To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

1 . A semiconductor chip, comprising:
 a substrate including a main surface, and a back surface opposite to the main surface;   a first pad formed in a layer over the main surface of the substrate;   a conductor portion formed in the layer, and spaced apart from the first pad; and   a protective film formed over the main surface of the substrate such that the protective film exposes the first pad, and such that the protective film covers the conductor portion,   wherein the conductor portion is formed along each edge of the main surface of the substrate in plan view, and   wherein the first pad is arranged at an outermost portion of the main surface.   
     
     
         2 . The semiconductor chip according to  claim 1 ,
 wherein an interlayer insulating film is arranged between the substrate and the layer,   wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film,   wherein the substrate is comprised of silicon, and   wherein dielectric constant of the low-dielectric constant film is lower than that of the substrate.   
     
     
         3 . The semiconductor chip according to  claim 1 ,
 wherein an interlayer insulating film is arranged between the substrate and the layer,   wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film,   wherein the substrate is comprised of silicon; and   wherein the low-dielectric constant film is more brittle than the substrate.   
     
     
         4 . The semiconductor chip according to  claim 1 ,
 wherein a second pad is formed in the layer, and spaced apart from the first pad and the conductor portion, and   wherein the protective film is formed over the main surface of the substrate such that the protective film exposes the second pad.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein the first pad is a test pad.   
     
     
         6 . The semiconductor chip according to  claim 1 ,
 wherein the substrate includes a side surface extending between the main surface and the back surface,   wherein the substrate has a modified region, and   wherein the modified region is contacted with the side surface of the substrate.   
     
     
         7 . A semiconductor chip, comprising:
 a substrate including a main surface, and a back surface opposite to the main surface;   a first pad formed in a layer over the main surface of the substrate;   a conductor portion formed in the layer, and spaced apart from the first pad; and   a protective film formed over the main surface of the substrate such that the protective film exposes the first pad, and such that the protective film covers the conductor portion,   wherein the conductor portion is formed along each edge of the main surface of the substrate in plan view, and   wherein the conductor portion is arranged at the inner side of the main surface than the first pad.   
     
     
         8 . The semiconductor chip according to  claim 7 ,
 wherein an interlayer insulating film is arranged between the substrate and the layer,   wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film,   wherein the substrate is comprised of silicon, and   wherein dielectric constant of the low-dielectric constant film is lower than that of the substrate.   
     
     
         9 . The semiconductor chip according to  claim 7 ,
 wherein an interlayer insulating film is arranged between the substrate and the layer,   wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film,   wherein the substrate is comprised of silicon; and   wherein the low-dielectric constant film is more brittle than the substrate.   
     
     
         10 . The semiconductor chip according to  claim 7 ,
 wherein a second pad is formed in the layer, and spaced apart from the first pad and the conductor portion, and   wherein the conductor portion and the second pad are arranged at the inner side of the main surface than the first pad.   
     
     
         11 . The semiconductor device according to  claim 7 ,
 wherein the first pad is a test pad.   
     
     
         12 . The semiconductor chip according to  claim 7 ,
 wherein the substrate includes a side surface extending between the main surface and the back surface,   wherein the substrate has a modified region, and   wherein the modified region is contacted with the side surface of the substrate.   
     
     
         13 . A semiconductor chip, comprising:
 a substrate including a main surface, and a back surface opposite to the main surface;   a plurality of first pads formed in a layer over the main surface of the substrate, and arranged along each edge of the main surface of the substrate in plan view;   a conductor portion formed in the layer, and spaced apart from the first pads; and   a protective film formed over the main surface of the substrate such that the protective film exposes the first pads, and such that the protective film covers the conductor portion,   wherein the conductor portion is formed along each edge of the main surface of the substrate in plan view, and   wherein each of the plurality of first pads is closer than the conductor portion is to each edge of the main surface of the substrate.   
     
     
         14 . The semiconductor chip according to  claim 13 ,
 wherein an interlayer insulating film is arranged between the substrate and the layer,   wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film,   wherein the substrate is comprised of silicon, and   wherein dielectric constant of the low-dielectric constant film is lower than that of the substrate.   
     
     
         15 . The semiconductor chip according to  claim 13 ,
 wherein an interlayer insulating film is arranged between the substrate and the layer,   wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film,   wherein the substrate is comprised of silicon; and   wherein the low-dielectric constant film is more brittle than the substrate.   
     
     
         16 . The semiconductor chip according to  claim 13 ,
 wherein a second pad is formed in the layer, and spaced apart from the first pads and the conductor portion, and   wherein each of the plurality of first pads is closer than the conductor portion and the second pad is to each edge of the main surface of the substrate.   
     
     
         17 . The semiconductor device according to  claim 13 ,
 wherein each of the first pad is a test pad.   
     
     
         18 . The semiconductor chip according to  claim 13 ,
 wherein the substrate includes a side surface extending between the main surface and the back surface,   wherein the substrate has a modified region, and   wherein the modified region is contacted with the side surface of the substrate.