Method of forming an insulator layer in a semiconductor structure and structures resulting therefrom

Abstract

An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.

1 .- 14 . (canceled) 
     
     
         15 . A semiconductor structure, comprising:
 a surface of a semiconductor wafer including a well structure of a first conductivity type;   a thin gate insulator layer over the surface of the semiconductor wafer;   a first spacer layer over a portion of the thin gate insulator layer;   a semiconductor substructure over a portion of the first spacer layer; and   a plurality of portions of a second spacer layer over a plurality of portions of the first spacer layer, wherein each portion of the second spacer layer is adjacent to a side-wall of the semiconductor substructure.   
     
     
         16 . The semiconductor structure of  claim 15 , wherein the semiconductor structure comprises an NMOS structure. 
     
     
         17 . The semiconductor structure of  claim 15 , wherein the semiconductor structure comprises a PMOS structure. 
     
     
         18 . The semiconductor structure of  claim 15 , wherein the thin gate insulator layer and the first spacer layer comprise a composite thick gate oxide layer. 
     
     
         19 . The semiconductor structure of  claim 15 , further comprising:
 a plurality of NLDD regions implanted in a P-well; and   a plurality of N+ regions implanted in each of the plurality of NLDD regions, wherein the semiconductor structure comprises an NMOS transistor.   
     
     
         20 . The semiconductor structure of  claim 15 , further comprising:
 a plurality of PLDD regions implanted in an N-well; and   a plurality of P+ regions implanted in each of the plurality of PLDD regions, wherein the semiconductor structure comprises a PMOS transistor.   
     
     
         21 . The semiconductor structure of  claim 15 , wherein at least one of the thin gate insulator layer and the first spacer layer includes a plurality of defects to trap holes. 
     
     
         22 . The semiconductor structure of  claim 15 , wherein the semiconductor structure comprises a first transistor, the thin gate insulator layer and the first spacer layer comprise a composite thermal oxide layer, and a threshold voltage shift of the first transistor is less than or equal to a threshold voltage shift of a second transistor including a thermal oxide layer, whereby a thickness of the composite thermal oxide layer is approximately equal to a thickness of the thermal oxide layer. 
     
     
         23 . An electronic system, comprising:
 a plurality of electronic circuits, wherein at least one electronic circuit includes at least one semiconductor structure comprising:   a surface of a semiconductor substrate including a well structure of a first conductivity type;   a thin gate insulator layer over the surface of the semiconductor substrate;   a first spacer layer over a portion of the thin gate insulator layer;   a semiconductor substructure over a portion of the first spacer layer; and   a plurality of portions of a second spacer layer over a plurality of portions of the first spacer layer, wherein each portion of the second spacer layer is adjacent to a side-wall of the semiconductor substructure.   
     
     
         24 . The electronic system of  claim 23 , wherein the at least one semiconductor structure comprises an NMOS structure. 
     
     
         25 . The electronic system of  claim 23 , wherein the at least one semiconductor structure comprises a PMOS structure. 
     
     
         26 . The electronic system of  claim 23 , wherein the thin gate insulator layer and the first spacer layer comprise a composite thick gate oxide layer. 
     
     
         27 . The electronic system of  claim 23 , wherein the at least one semiconductor structure comprises a radiation-hardened transistor. 
     
     
         28 . The electronic system of  claim 23 , wherein the electronic system comprises an electronic system for a space-based platform. 
     
     
         29 . The electronic system of  claim 23 , wherein the first spacer layer includes a plurality of defects to trap holes. 
     
     
         30 . A semiconductor structure, comprising:
 a semiconductor substrate;   a thin insulator layer over the semiconductor substrate;   a first semiconductor substructure over the thin insulator layer;   a spacer layer over a portion of the thin insulator layer; and   a second semiconductor substructure over a portion of the spacer layer.   
     
     
         31 . The semiconductor structure of  claim 30 , wherein the thin insulator layer comprises a thin gate oxide layer. 
     
     
         32 . The semiconductor structure of  claim 30 , wherein the first semiconductor substructure comprises a gate structure. 
     
     
         33 . The semiconductor structure of  claim 30 , wherein the thin insulator layer and the spacer layer comprise a thick gate insulator layer. 
     
     
         34 . The semiconductor structure of  claim 30 , wherein the thin insulator layer and the spacer layer comprise a composite thick gate oxide layer. 
     
     
         35 . The semiconductor structure of  claim 30 , wherein the semiconductor structure comprises at least one IGFET. 
     
     
         36 .- 42 . (canceled)