Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation

Abstract

A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.

What is claimed is: 
     
         1 . A method for forming a transistor, comprising:
 providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate comprising source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions;   providing a carrier gas carrying alane precursor in a reactor at a predetermined pressure while the III-V substrate has a predetermined temperature; and   growing metal contacts on the source/drain regions using the alane precursor.   
     
     
         2 . The method of  claim 1 , further comprising forming the source/drain regions at least by implanting a dopant into the III-V substrate. 
     
     
         3 . The method of  claim 2 , wherein the dopant comprises one or more of Si, Ge, S, Se, and Te for n+ implantation and one or more of C, Mg, Be, and Zn for p+ implantation. 
     
     
         4 . The method of  claim 1 , further comprising performing thermal annealing of the III-IV substrate prior to the growing of the metal contacts. 
     
     
         5 . The method of  claim 1 , wherein the predetermined temperature is between 150 Centigrade (C) and 360 C. 
     
     
         6 . The method of  claim 5 , wherein the alane precursor comprises dimethyl-ethyl amine alane (DMEAA). 
     
     
         7 . The method of  claim 5 , wherein pressure of the reactor is between 0.001 millibar (mbar) to 100 mbar and a flow rate of the alane precursor is between 0.1 to 100 micro-mole per minute. 
     
     
         8 . The method of  claim 1 , wherein the III-V substrate comprises one or more of GaAs, InGaAs, GaSb, and InP. 
     
     
         9 . The method of  claim 1 , used in the fabrication of integrated circuit chips. 
     
     
         10 . A method for forming a transistor, comprising:
 providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate comprising source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions;   growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions comprised of III-V semiconductor material; and   growing metal contacts on the grown raised source/drain regions using a carrier gas carrying alane precursor in a reactor at a predetermined pressure;   wherein:   growing raised source/drain regions on the source/drain regions further comprises providing a first carrier gas carrying a III-V material source and a dopant source in a reactor at a first predetermined pressure while the III-V substrate has a first predetermined temperature;   growing raised source/drain regions on the source/drain regions further comprises, without breaking vacuum in the reactor after growing the raised source/drain regions, providing a second carrier gas carrying a III-V material source and a dopant source in the reactor at a second predetermined pressure while the III-V substrate has a second predetermined temperature.   
     
     
         11 . The method of  claim 10 , further comprising forming the source/drain regions at least by implanting a dopant into the III-V substrate. 
     
     
         12 . The method of  claim 11 , wherein the dopant comprises one or more of Si, Ge, S, Se, and Te for n+ implantation and one or more of C, Mg, Be, and Zn for p+ implantation. 
     
     
         13 . The method of  claim 10 , wherein growing raised source/drain regions on the source/drain regions further comprises providing a carrier gas carrying a III-V material source and a dopant source in the reactor at the predetermined pressure while the III-V substrate has a predetermined temperature. 
     
     
         14 . The method of  claim 13 , further comprising performing thermal annealing of the III-IV substrate in the reactor without breaking vacuum in the reactor. 
     
     
         15 . The method of  claim 13 , wherein the III-V material source comprises one or more of AsH 3  and tributylarsene. 
     
     
         16 . The method of  claim 10 , wherein either the first or second predetermined temperature is between 150 Centigrade (C) and 360 C. 
     
     
         17 . The method of  claim 16 , wherein the alane precursor comprises dimethyl-ethyl amine alane (DMEAA). 
     
     
         18 . The method of  claim 16 , wherein pressure of the reactor is between 0.001 millibar (mbar) to 100 mbar and a flow rate of the alane precursor is between 0.1 to 100 micro-mole per minute. 
     
     
         19 . The method of  claim 10 , wherein the III-V substrate comprises one or more of GaAs, InGaAs, GaSb, and InP. 
     
     
         20 . The method of  claim 10 , used in the fabrication of integrated circuit chips.