Semiconductor integrated circuit device and system using the same

Abstract

A processor system, includes a first central processing unit (CPU) that executes a redundant instruction set; and a second CPU that executes the redundant instruction set, wherein before the second CPU executes a redundant instruction among the redundant instruction set, the first CPU is able to execute n (n is a predetermined integer number) redundant instructions among the redundant instruction set, and wherein when an exception occurs during execution of the redundant instruction set in the first CPU, the first CPU executes an instruction for the exception as a non-redundant instruction.

What is claimed is: 
     
         1 . A processor system, comprising:
 a first central processing unit (CPU) that executes a redundant instruction set; and   a second CPU that executes the redundant instruction set,   wherein before the second CPU executes a redundant instruction among the redundant instruction set, the first CPU is able to execute n (n is a predetermined integer number) redundant instructions among the redundant instruction set, and   wherein when an exception occurs during execution of the redundant instruction set in the first CPU, the first CPU executes an instruction for the exception as a non-redundant instruction.   
     
     
         2 . The processor system according to  claim 1 , wherein the instruction for the exception does not count as the n redundant instructions. 
     
     
         3 . The processor system according to  claim 1 , wherein the redundant instruction set includes a read instruction and a write instruction. 
     
     
         4 . The processor system according to  claim 1 , wherein the redundant instruction set is included in a thread. 
     
     
         5 . The processor system according to  claim 1 , wherein the first and second CPU are the same architecture. 
     
     
         6 . The processor system according to  claim 1 , wherein the exception occurs when at least one of a memory error, a zero division, an execution of undefined instruction occurs in the first CPU. 
     
     
         7 . The processor system according to  claim 1 , wherein the first and second CPUs are included in the same semiconductor device.