Receiver circuit

Abstract

A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a positive intermediate output signal and a negative intermediate output signal. The second amplification unit is configured to receive the positive intermediate output signal as a positive input signal and the negative intermediate signal as a negative input signal, differentially amplify the positive and negative input signals and generate a positive output signal and a negative output signal. The first equalizing unit is configured to control the level of the negative intermediate output signal in response to the positive output signal. The second equalizing unit is configured to control the level of the positive intermediate output signal in response to the negative output signal

What is claimed is: 
     
         1 . A receiver circuit comprising:
 a first amplification unit configured to differentially amplify an input signal and a reference signal and generate a positive intermediate output signal and a negative intermediate output signal;   a second amplification unit configured to receive the positive intermediate output signal as a positive input signal and the negative intermediate signal as a negative input signal, differentially amplify the positive and negative input signals and generate a positive output signal and a negative output signal;   a first equalizing unit configured to control the level of the negative intermediate output signal in response to the positive output signal; and   a second equalizing unit configured to control the level of the positive intermediate output signal in response to the negative output signal.   
     
     
         2 . The receiver circuit according to  claim 1 , wherein the first equalizing unit drops the negative intermediate output signal by a predetermined level, when the positive output signal is at a high level. 
     
     
         3 . The receiver circuit according to  claim 2 , wherein the first equalizing unit comprises:
 a first driver configured to drive a first node to a ground voltage in response to the positive output signal; and   a first switch configured to connect the first node to the negative intermediate output signal in response to the reference signal.   
     
     
         4 . The receiver circuit according to  claim 1 , wherein the second equalizing unit drops the positive intermediate output signal by a predetermined level, when the negative the output signal is at a high level. 
     
     
         5 . The receiver circuit according to  claim 4 , wherein the second equalizing unit comprises:
 a second driver configured to drive a second node to the ground voltage in response to the negative output signal; and   a second switch configured to connect the second node and the positive intermediate output signal in response to the input signal.   
     
     
         6 . The receiver circuit according to  claim 1 , further comprising a delay unit configured to control a time at which the positive and negative output signals are provided to the first and second equalizing units. 
     
     
         7 . A receiver circuit comprising:
 a first amplification unit configured to differentially amplify an input signal and a reference signal and generate positive and negative intermediate output signals;   a second amplification unit configured to generate positive and negative output signals in response to the positive and negative intermediate output signals; and   a de-emphasis driver configured to drop the positive intermediate output signal by a predetermined level when the negative output signal is at a high level, and drop the negative intermediate output signal by a predetermined level when the positive output signal is at a high level.   
     
     
         8 . The receiver circuit according to  claim 7 , wherein the de-emphasis driver comprises:
 a first equalizing unit configured to control the level of the negative intermediate output signal in response to the positive output signal; and   a second equalizing unit configured to control the level of the positive intermediate output signal in response to the negative output signal.   
     
     
         9 . The receiver circuit according to  claim 8 , wherein the first equalizing unit comprises:
 a first driver configured to drive a first node to a ground voltage in response to the positive output signal; and   a first switch configured to connect the first node to the negative intermediate output signal in response to the reference signal.   
     
     
         10 . The receiver circuit according to  claim 8 , wherein the second equalizing unit comprises:
 a second driver configured to drive a second node to a ground voltage in response to the negative output signal; and   a second switch configured to connect the second node to the positive intermediate output signal in response to the input signal.   
     
     
         11 . The receiver circuit according to  claim 7 , further comprising a delay unit configured to control a time at which the positive and negative output signals are provided to the de-emphasis driver. 
     
     
         12 . A receiver circuit comprising:
 a first amplification unit configured to differentially amplify an input signal and a reference signal and generate positive and negative intermediate output signals;   a second amplification unit configured to generate positive and negative output signals in response to the first and second intermediate output signals; and   a de-emphasis driver configured to drop the positive and negative intermediate output signals by a predetermined level in response to the positive output signal, the negative output signal, the input signal and the reference signal.   
     
     
         13 . The receiver circuit according to  claim 12 , wherein the de-emphasis driver comprises:
 a first driving unit configured to control the levels of the positive and negative intermediate output signals in response to the positive output signal, the input signal and the reference signal; and   a second driving unit configured to control the levels of the positive and negative intermediate output signals in response to the negative output signal, the input signal and the reference signal.   
     
     
         14 . The receiver circuit according to  claim 13 , wherein the first driving unit drops one of the positive and negative intermediate output signals by a predetermined level when the positive output signal is at a high level according to the level of the input signal. 
     
     
         15 . The receiver circuit according to  claim 13 , wherein the first driving unit comprises:
 a third driver configured to drive a third node to a ground voltage in response to the positive output signal; and   a third switch configured to connect the third node to the positive and negative intermediate output signals in response to the input signal and the reference signal.   
     
     
         16 . The receiver circuit according to  claim 13 , wherein the second driving unit drops the positive and negative intermediate output signals by a predetermined level when the negative output signal is at a high level according to the level of the input signal. 
     
     
         17 . The receiver circuit according to  claim 13 , wherein the second driving unit comprises:
 a fourth driver configured to drive a fourth node to a ground voltage in response to the negative output signal; and   a fourth switch configured to connect the fourth node to the positive and negative intermediate output signals in response to the input signal and the reference signal.   
     
     
         18 . The receiver circuit according to  claim 12 , further comprising a delay unit configured to control a time at which the output signal is provided to the de-emphasis driver.