Semiconductor device

Abstract

A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate having a main surface and a back surface;   a drain region of a first conduction type formed at the back surface of the semiconductor substrate;   an epitaxial layer of the first conduction type on the drain region, wherein impurity concentration of the epitaxial layer is lower than that of the drain region;   a base region of a second conduction type opposite to the first conduction type formed in the epitaxial layer and provided over the drain region;   a plurality of source regions of the first conduction type(N) provided in the base region;   an outer peripheral well region of the second conduction type provided in the epitaxial layer so as to cover the outer peripheral end of the base region and having a concentration of impurity lower than that of the base region;   a buried electrode situated in the base region in a plan view, and buried in the base region and the epitaxial layer in a cross sectional view;   a plurality of gate electrodes situated in the base region in a plan view, electrically connected to the buried electrode, and buried in the base region and the epitaxial layer in a cross sectional view so as to be adjacent to the source regions respectively;   a gate interconnect provided over the main surface of the semiconductor substrate so as to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode by way of a first contact plug; and   a grounding electrode provided over the main surface of the semiconductor substrate and connected by way of a second contact plug to a portion of the outer peripheral well region apart from the gate interconnect in a plan view,   wherein a buried electrode is apart from the outer peripheral well region.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the buried electrode is provided such that the lower end of the buried electrode is deeper than the lower end of the base region.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the buried electrode has a width larger than that of the gate electrode.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the depth of the trench for the buried electrode is larger than the depth of the trench for the gate electrode.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein
 the buried electrode is provided to the inside of the outer peripheral well region formed in a frame-like shape being spaced from the outer peripheral well region.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein the grounding electrode has an inner part situated inward of the buried electrode in the base region in a plan view and a second protrusion part extending from the inner part to the outer peripheral well, and connected at the second protrusion part to the second contact.   
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein the gate interconnect has an outer part formed so as to overlap the outer edge of the outer peripheral well region and a first protrusion part extending from the outer part to the buried electrode, and connected at the first protrusion part to the first contact.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein a plurality of the first protrusion parts are provided to the gate interconnect, and   wherein a plurality of the second protrusion parts are provided to the grounding electrode so that the first protrusion parts and the second protrusion parts are situated alternately at least in a portion of the region.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the plurality of gate electrodes are arranged parallel to each other and each of the ends thereof is connected to the buried electrode, and   wherein the first contact is provided so as to be connected to the intersection where the buried electrode and the gate electrode are disposed on the cross each other.   
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein a device isolation film that overlaps the outer edge of the outer peripheral well region is formed in the epitaxial layer.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein the lower end of the buried electrode is situated nearer to the back surface of the semiconductor substrate than the lower end of the gate electrode.