Magnetic memory device

Abstract

According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area.

What is claimed is: 
     
         1 . A magnetic memory device comprising:
 a semiconductor substrate;   a memory cell array on the semiconductor substrate, the memory cell array including magnetoresistive elements;   a first magnetic section provided away from the memory cell array; and   a second magnetic section surrounding the memory cell array and the first magnetic section.   
     
     
         2 . The device of  claim 1 , wherein the second magnetic section surrounds the memory cell array and the first magnetic section in a first direction and a second direction different from the first direction. 
     
     
         3 . The device of  claim 1 , wherein the first magnetic section includes a Co—Cr-based alloy, an Sm—Co-based alloy, a Co—Pt-based alloy, an Fe—Pt-based alloy, an Nd—Fe-based alloy, an Mn—Al-based alloy, an Al—Ni—Co-based alloy, a Ba ferrite-based oxide, or a Co ferrite-based oxide. 
     
     
         4 . The device of  claim 1 , wherein the second magnetic section includes Ni, Fe, Co, a Ni—Fe alloy, a Fe—Co alloy, or Fe containing Ni, Mn or Zn. 
     
     
         5 . The device of  claim 1 , further comprising an insulating layer and a wiring, 
       wherein the first magnetic section provided away from the memory cell array via the insulating layer and the wiring. 
     
     
         6 . The device of  claim 1 , further comprising resin provided between the second magnetic section and the memory cell array. 
     
     
         7 . The device of  claim 1 , wherein each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer between the reference layer and the storage layer. 
     
     
         8 . The device of  claim 7 , wherein the first magnetic section generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer. 
     
     
         9 . The device of  claim 8 , wherein the second magnetic section functions as a closed magnetic path of the first magnetic field. 
     
     
         10 . The device of  claim 1 , wherein the first magnetic section includes a permanent magnet. 
     
     
         11 . The device of  claim 1 , wherein the first magnetic section includes a magnetic layer with an invariable magnetization. 
     
     
         12 . The device of  claim 7 , wherein the reference layer and the storage layer has a perpendicular magnetization which is perpendicular to a surface of the semiconductor substrate, and
 the first magnetic field has magnetic lines which are perpendicular to the surface of the semiconductor substrate in the memory cell array.   
     
     
         13 . The device of  claim 7 , wherein the reference layer and the storage layer has a in-plane magnetization which is parallel to a surface of the semiconductor substrate, and
 the first magnetic field has magnetic lines which are parallel to the surface of the semiconductor substrate in the memory cell array.   
     
     
         14 . The device of  claim 1 , further comprising a memory chip including the semiconductor substrate, the memory cell array, and the first magnetic section. 
     
     
         15 . The device of  claim 14 , wherein the first magnetic section is a magnetic layer stacked on the memory cell array and shared by the magnetoresistive elements. 
     
     
         16 . The device of  claim 15 , wherein the memory chip includes a peripheral circuit, and
 the magnetic layer is provided in the memory cell array and not provided in the peripheral circuit.   
     
     
         17 . The device of  claim 16 , wherein the peripheral circuit includes an external terminal connected to an external element which is provided out of the memory chip. 
     
     
         18 . The device of  claim 15 , further comprising a bit line connected to the magnetoresistive elements, the magnetic layer being stacked on the bit line and extending in a direction in which the bit line extends. 
     
     
         19 . The device of  claim 15 , further comprising a bit line connected to the magnetoresistive elements, the bit line being stacked on the magnetic layer extending in a direction in which the bit line extends. 
     
     
         20 . The device of  claim 1 , further comprising a memory chip including the semiconductor substrate and the memory cell array,
 wherein the first magnetic section is provided out of the memory chip.   
     
     
         21 . The device of  claim 20 , wherein the first magnetic section is a magnetic layer provided on the memory chip and shared by the magnetoresistive elements. 
     
     
         22 . The device of  claim 21 , wherein the magnetic layer includes a permanent magnet. 
     
     
         23 . The device of  claim 20 , wherein the first magnetic section is a magnetic layer provided under the memory chip and shared by the magnetoresistive elements. 
     
     
         24 . The device of  claim 23 , wherein the magnetic layer includes a permanent magnet. 
     
     
         25 . The device of  claim 1 , further comprising:
 a memory chip including the semiconductor substrate and the memory cell array; and   a circuit board on which the memory chip is mounted,   wherein the first magnetic section is provided in the circuit board.   
     
     
         26 . The device of  claim 25 , wherein the circuit board comprises wiring layers, and
 the first magnetic section is a magnetic layer provided in one of the wiring layers and shared by the magnetoresistive elements.   
     
     
         27 . The device of  claim 26 , wherein the magnetic layer has an invariable magnetization.