Removable and replaceable tap domain selection circuitry

Abstract

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

1 . An integrated circuit comprising:
 A. a bypass test data in lead;   B. a bypass test data out lead;   C. a one-bit bypass register having a test data input coupled to the bypass test data in lead, a test data output coupled to the bypass test data out lead, and a clock input;   D. a ClockDR lead;   E. a ClockIR lead; and   F. gating circuitry having an input coupled to the ClockDR lead, an input coupled to the ClockIR lead, and an output connected to the clock input.   
     
     
         2 . The integrated circuit of  claim 1  including:
 an IC test data input coupled to the bypass test data in lead; and 
 an IC test data output coupled to the bypass test data out lead. 
 
     
     
         3 . The integrated circuit of  claim 1  including;
 an IC test data input; 
 an IC test data output; and 
 linking circuitry coupling the IC test data input to the bypass test data in lead, and coupling the bypass test data out lead to the IC test data output. 
 
     
     
         4 . The integrated circuit of  claim 1  including;
 an IC test data input; 
 an IC test data output; 
 input linking circuitry coupling the IC test data input to the bypass test data in lead; and 
 output linking circuitry coupling the bypass test data out lead to the IC test data output. 
 
     
     
         5 . The integrated circuit of  claim 1  including;
 an IC test clock input; 
 an IC test mode select input; and 
 test access port state machine circuitry having a clock input coupled with the IC test clock input, a test mode select input coupled with the IC test mode select input, a ClockDR output coupled to the ClockDR lead, and a ClockIR output coupled to the ClockIR lead. 
 
     
     
         6 . The integrated circuit of  claim 1  including;
 an IC test clock input; 
 an IC test mode select input; 
 test access port state machine circuitry having a test clock input, a test mode select input, a ClockDR output coupled to the ClockDR lead, and a ClockIR output coupled to the ClockIR lead; and 
 input linking circuitry coupling the IC test clock input to the test clock input, and coupling the IC test mode select input to the test mode select input. 
 
     
     
         7 . The integrated circuit of  claim 1  in which the gating circuitry includes an OR gate circuit. 
     
     
         8 . The integrated circuit of  claim 1  in which the one-bit bypass register is a D-type flip-flop. 
     
     
         9 . The integrated circuit of  claim 1  including:
 an IC test data input; 
 an IC test data output; 
 input linking circuitry coupling the IC test data input to the bypass test data in lead and having a control input; 
 output linking circuitry coupling the bypass test data out lead to the IC test data output, and having a control input; and 
 tap domain selection circuitry coupled between the IC test data input and the IC test data output and having control outputs coupled to the control inputs of the input linking circuitry and to the output linking circuitry. 
 
     
     
         10 . The integrated circuit of  claim 1  including:
 an IC test data input; 
 an IC test data output; 
 input linking circuitry coupling the IC test data input to the bypass test data in lead and having a control input; 
 output linking circuitry coupling the bypass test data out lead to the IC test data output, and having a control input; and 
 tap domain selection circuitry coupled between the IC test data input and the input linking circuitry and having control outputs coupled to the control inputs of the input linking circuitry and the output linking circuitry. 
 
     
     
         11 . The integrated circuit of  claim 1  including:
 an IC test data input; 
 an IC test data output; 
 input linking circuitry coupling the IC test data input to the bypass test data in lead and having a control input; 
 output linking circuitry coupling the bypass test data out lead to the IC test data output, and having a control input; and 
 tap domain selection circuitry coupled between the output linking circuitry and the IC test data output, and having control outputs coupled to the control inputs of the input linking circuitry and the output linking circuitry. 
 
     
     
         12 . The integrated circuit of  claim 1  including:
 an IC test data input; 
 an IC test data output; 
 test access port domain circuitry having a domain test data input and a domain test data output; 
 input linking circuitry selectively coupling the IC test data input to the bypass test data in lead and the domain test data input, and having a control input; 
 output linking circuitry selectively coupling the bypass test data out lead and the domain test data output to the IC test data output, and having a control input; and 
 test access port domain selection circuitry coupled between the IC test data input and the IC test data output and having control outputs coupled to the control inputs of the input linking circuitry and to the output linking circuitry. 
 
     
     
         13 . The integrated circuit of  claim 1  including a test access port state machine having states of ShiftDR and ShiftIR and having a ClockDR output coupled to the ClockDR lead and a Clock IR output coupled to the ClockIR lead. 
     
     
         14 . An integrated circuit comprising:
 A. a test data in lead;   B. a test data out lead;   C. a ClockDR lead;   D. a ClockIR lead; and   E. one-bit bypass register circuitry having a bypass test data input coupled to the test data in lead, a bypass test data output coupled to the test data out lead, an input coupled to the ClockDR lead, and an input coupled to the ClockIR lead, the one-bit bypass register circuitry providing a single scan path register bit between the test data in lead and the test data out lead during both instruction register and data register scan operations.   
     
     
         15 . The integrated circuit of  claim 14  including linking circuitry coupling the test data in lead to the bypass test data input, and coupling the bypass test data output to the test data out lead. 
     
     
         16 . The integrated circuit of  claim 14  including input linking circuitry coupling the test data in lead to the bypass test data input, and output linking circuitry coupling the bypass test data output to the test data out lead. 
     
     
         17 . The integrated circuit of  claim 14  including;
 a test clock input; 
 a test mode select input; and 
 test access port state machine circuitry having a clock input coupled with the test clock input, a test mode select input coupled with the test mode select input, a ClockDR output coupled to the ClockDR lead, and a ClockIR output coupled to the ClockIR lead. 
 
     
     
         18 . The integrated circuit of  claim 14  including;
 a test clock input; 
 a test mode select input; 
 test access port state machine circuitry having a test clock input, a test mode select input, a ClockDR output coupled to the ClockDR lead, and a ClockIR output coupled to the ClockIR lead; and 
 input linking circuitry coupling the test clock input to the test clock input, and coupling the test mode select input to the test mode select input. 
 
     
     
         19 . The integrated circuit of  claim 14  in which the one-bit bypass register circuitry includes an OR gate circuit having an input connected to the ClockDR lead, an input connected to the ClockIR lead, and a clock output. 
     
     
         20 . The integrated circuit of  claim 1  in which the one-bit bypass register circuitry includes a D-type flip-flop having an input connected to the bypass test data input, an output connected to the bypass test data output, and a clock input. 
     
     
         21 . The integrated circuit of  claim 1  including:
 input linking circuitry coupling the test data input to the bypass test data input and having a control input; 
 output linking circuitry coupling the bypass test data output to the test data out lead, and having a control input; and 
 TAP domain selection circuitry coupled between the test data in lead and the test data out lead and having control outputs coupled to the control inputs of the input linking circuitry and the output linking circuitry. 
 
     
     
         22 . The integrated circuit of  claim 14  including:
 input linking circuitry coupling the test data in lead to the bypass test data input and having a control input; 
 output linking circuitry coupling the bypass test data output to the test data out lead, and having a control input; and 
 TAP domain selection circuitry coupled between the test data in lead and the input linking circuitry and having control outputs coupled to the control inputs of the input linking circuitry and the output linking circuitry. 
 
     
     
         23 . The integrated circuit of  claim 14  including:
 input linking circuitry coupling the test data in lead to the bypass test data input and having a control input; 
 output linking circuitry coupling the bypass test data output to the test data out lead and having a control input; and 
 TAP domain selection circuitry coupled between the output linking circuitry and the test data out lead, and having control outputs coupled to the control inputs of the input linking circuitry and the output linking circuitry. 
 
     
     
         24 . The integrated circuit of  claim 14  including:
 test access port domain circuitry having a domain test data input and a domain test data output; 
 input linking circuitry selectively coupling the test data in lead to the bypass test data input and to the domain test data input, and having a control input; 
 output linking circuitry selectively coupling the bypass test data output and the domain test data output to the test data out lead, and having a control input; and 
 test access port domain selection circuitry coupled between the test data in lead and the test data out lead and having control outputs coupled to the control inputs of the input linking circuitry and the output linking circuitry. 
 
     
     
         25 . The integrated circuit of  claim 14  including a test access port state machine having states of ShiftDR and ShiftIR and having a ClockDR output coupled to the ClockDR lead and a Clock IR output coupled to the ClockIR lead. 
     
     
         26 . A process of operating an integrated circuit comprising:
 selecting bypass one-bit register circuitry as a single scan path register bit between a test data input lead and a test data output lead of the integrated circuit;   operating the bypass one-bit register circuitry during a scan operation of instruction register circuitry of the integrated circuit; and   operating the bypass one-bit register circuitry during a scan operation of a data register circuitry of the integrated circuit.   
     
     
         27 . The process of  claim 26  in which the selecting bypass one-bit register circuitry includes de-selecting the instruction register circuitry. 
     
     
         28 . The process of  claim 26  in which the selecting bypass one-bit register circuitry includes de-selecting the data register circuitry. 
     
     
         29 . The process of  claim 26  in which the operating the bypass one-bit register circuitry during a scan operation of instruction register circuitry of the integrated circuit includes not operating the instruction register circuitry. 
     
     
         30 . The process of  claim 26  in which the operating the bypass one-bit register circuitry during a scan operation of data register circuitry of the integrated circuit includes not operating the data register circuitry. 
     
     
         31 . The process of  claim 26  in which the operating the bypass one-bit register circuitry during a scan operation of instruction register circuitry of the integrated circuit includes operating the bypass one-bit register circuitry in response to a test clock signal and a test mode select signal applied to a test access port state machine. 
     
     
         32 . The process of  claim 26  in which the operating the bypass one-bit register circuitry during a scan operation of data register circuitry of the integrated circuit includes operating the bypass one-bit register circuitry in response to a test clock signal and a test mode select signal applied to a test access port state machine. 
     
     
         33 . The process of  claim 26  in which the selecting bypass one-bit register circuitry as a single scan path register bit between a test data input lead and a test data output lead of the integrated circuit includes selecting the bypass one-bit register circuitry in response to operating TAP domain selection circuitry coupled between the test data input lead and the test data output lead and operating linking circuitry coupled between the bypass one-bit register circuitry and the data input lead and between the bypass one-bit register circuitry and the test data output lead.