Image pickup circuit

Abstract

An image pickup circuit including a plurality of circuit blocks. Each of the plurality of circuit blocks includes a plurality of comparing elements, a single counter, and a plurality of storage units. Each of the comparing elements compares a pixel signal supplied through a vertical signal line connected to vertically aligned pixels in a plurality of pixels arranged in a matrix, and a slope signal whose voltage is changed from an initial voltage at a constant slope. The counter counts an elapsed time since a voltage of the slope signal starts to change from the initial voltage. Each of the storage units stores a count value obtained by the counter in accordance with a comparison result of the comparator, the count value corresponding to an elapsed time until the voltage of the slope signal is changed from the initial voltage to a voltage coinciding with the pixel signal.

1 - 5 . (canceled) 
     
     
         6 . An image pickup circuit comprising:
 a plurality of pixels arranged in a matrix of horizontally extending pixel rows and vertically extending pixel columns;   a plurality of vertical signal lines respectively connected to pixels in the pixel columns; and   a plurality of circuit blocks aligned along the horizontal direction,   wherein the vertical signal lines include a first vertical signal line connected to first pixels in a first pixel column, and a second vertical signal line connected to second pixels in a second pixel column adjacent to the first pixel column, and   wherein each of the plurality of circuit blocks includes:
 (a) comparison circuitry configured to compare a pixel signal supplied through at least one of the first and second vertical signal lines and a reference signal having a voltage that is changed from an initial voltage; and 
 (b) a counter unit for counting an elapsed time since a voltage of the reference signal starts to change from the initial voltage, wherein the counter unit is shared among the first and second pixel columns. 
   
     
     
         7 . The image pickup circuit of  claim 6 , further comprising storage units including at least one of latch circuits and sample-hold circuits. 
     
     
         8 . The image pickup circuit of  claim 6 , wherein each circuit block further includes a selection circuit configured to select which pixel signals are supplied from the plurality of vertical signal lines. 
     
     
         9 . The image pickup circuit of  claim 6 , wherein the comparison circuitry is shared by at least two pixel columns and the counter unit is shared by at least two comparison circuitries. 
     
     
         10 . An image pickup circuit comprising:
 a pixel array including first pixels and second pixels;   a plurality of vertical signal lines including a first vertical signal line and a second vertical signal line adjacent to the first vertical signal line;   a reference voltage generation circuit; and   a plurality of circuit blocks,   
       wherein
 the first vertical signal line is connected to the first pixels, 
 the second vertical signal line is connected to the second pixels, 
 each of the circuit blocks includes:
 (a) comparison circuitry configured to compare a pixel signal supplied through first or second vertical signal lines and a reference signal supplied from the reference voltage generation circuit; and 
 (b) a counter unit associated with the comparison circuitry, wherein the counter unit is shared among the first and second pixels. 
 
 
     
     
         11 . The image pickup circuit of  claim 10 , further comprising storage units including at least one of latch circuits and sample-hold circuits. 
     
     
         12 . The image pickup circuit of  claim 10 , wherein each circuit block further includes a selection circuit configured to select which pixel signals are supplied from the plurality of vertical signal lines to a selected one of the circuit blocks. 
     
     
         13 . The image pick up circuit of  claim 10 , wherein the comparison circuitry is shared by at least two pixel columns and the counter unit is shared by at least two comparison circuitries. 
     
     
         14 . An image pickup circuit comprising:
 a pixel array including first pixels and second pixels;   a plurality of vertical signal lines including a first, second, third, and fourth vertical signal lines;   a reference voltage generation circuit; and   a plurality of circuit blocks,   
       wherein
 the second vertical signal line is adjacent to the first vertical signal line, 
 the third vertical signal line is adjacent to the second vertical signal line, 
 the fourth vertical signal line is adjacent to the third vertical signal line, 
 each of the circuit blocks includes:
 (a) a first comparison circuitry configured to compare a pixel signal supplied through first or second vertical signal lines and a reference signal supplied from the reference voltage generation circuit; 
 (b) a second comparison circuitry configured to compare a pixel signal supplied through third or fourth vertical signal lines and the reference signal supplied from the reference voltage generation circuit; and 
 (c) a counter unit associated with the first comparison circuitry and the second comparison circuitry. 
 
 
     
     
         15 . The image pickup circuit of  claim 14 , further comprising storage units including at least one of latch circuits and sample-hold circuits. 
     
     
         16 . The image pickup circuit of  claim 14 , wherein each circuit block further includes a selection circuit configured to select which pixel signals are supplied from the plurality of vertical signal lines to supply to a selected one of the circuit blocks. 
     
     
         17 . The image pick up circuit of  claim 14 , wherein the comparison circuitry is shared by at least two pixel columns and the counter unit is shared by at least two of the comparison circuitries. 
     
     
         18 . An imaging device comprising:
 a pixel array including a plurality of pixel units arranged in columns and rows;   a reference voltage generation circuit; and   a circuit block including:
 (a) a first circuit including:
 a first plurality of comparators, and 
 a first counter unit configured to connect to the first plurality of comparators; 
 
 (b) a second circuit including:
 a second plurality of comparators, and 
 a second counter unit configured to connect to the second plurality of comparators; and 
 a first readout circuit adjacent to a second read out circuit. 
 
   
     
     
         19 . The imaging device according to  claim 18 , further comprising a plurality of vertical signal lines configured to respectively connect to the plurality of pixel units, wherein the plurality of pixel units is configured to connect to the circuit block through the plurality of vertical signal lines. 
     
     
         20 . The imaging device according to  claim 19 , wherein a first vertical signal line of the plurality of vertical signal lines is configured to connect to a first comparator of the first plurality of comparators and a second vertical signal line of the plurality of the vertical signal lines is configured to connect to a second comparator of the first plurality of comparators. 
     
     
         21 . The imaging device according to  claim 20 , wherein a third vertical signal line of the plurality of the vertical signal lines is configured to connect to a third comparator of the second plurality of comparators and a fourth vertical signal line of the plurality of the vertical signal lines is configured to connect to a fourth comparator of the second plurality of comparators. 
     
     
         22 . The imaging device according to  claim 21 , wherein, a first vertical signal line of the plurality of vertical signal lines is shared with a first comparator and a second comparator of the first plurality of comparators. 
     
     
         23 . The imaging device according to  claim 22 , wherein a second vertical signal line of the plurality of vertical signal lines is shared with a third comparator and a fourth comparator of the second plurality of comparators. 
     
     
         24 . The imaging device according to  claim 23 , further comprising a first switching circuit, wherein a first pixel unit and a second pixel unit of the plurality of pixel units is configured to connect to the first comparator through the first switching circuit. 
     
     
         25 . The imaging device according to  claim 24 , further comprising a second switching circuit, wherein a third pixel unit and a fourth pixel unit of the plurality of pixel units is configured to connect to the third comparator through the second switching circuit. 
     
     
         26 . The imaging device according to  claim 25 , wherein the first pixel unit is adjacent to the second pixel unit. 
     
     
         27 . The imaging device according to  claim 26 , wherein the third pixel unit is adjacent to the fourth pixel unit. 
     
     
         28 . An electronic apparatus comprising;
 an optical system;   an imaging device including:
 a pixel array including a plurality of pixel units arranged in columns and rows; 
 a reference voltage generation circuit; and 
 a circuit block, wherein 
   the circuit block includes:
 (a) a first circuit including:
 a first plurality of comparators; and 
 a first counter unit configured to connect to the first plurality of comparators; 
 
 (b) a second circuit including:
 a second plurality of comparators; and 
 a second counter unit configured to connect to the second plurality of comparators, and 
 a first readout circuit adjacent to a second read out circuit. 
 
   
     
     
         29 . The electronic apparatus according to  claim 28 , further comprising a plurality of vertical signal lines configured to respectively connect to the plurality of the pixel units, wherein the plurality of pixel units is configured to connect to the circuit block through the plurality of vertical signal lines. 
     
     
         30 . The electronic apparatus according to  claim 29 , wherein a first vertical signal line of the plurality of vertical signal lines is configured to connect to a first comparator of the first plurality of comparators and a second vertical signal line of the plurality of vertical signal lines is configured to connect to a second comparator of the first plurality of comparators. 
     
     
         31 . The electronic apparatus according to  claim 30 , wherein a third vertical signal line of the plurality of vertical signal lines is configured to connect to a third comparator of the second plurality of comparators and a fourth vertical signal line of the plurality of the vertical signal lines is configured to connect to a fourth comparator of the second plurality of comparators. 
     
     
         32 . The electronic apparatus according to  claim 31 , wherein, a first vertical signal line of the plurality of vertical signal lines is shared with a first comparator and a second comparator of the first plurality of comparators. 
     
     
         33 . The electronic apparatus according to  claim 32 , wherein a second vertical signal line of the plurality of vertical signal lines is shared with a third comparator and a fourth comparator of the second plurality of comparators. 
     
     
         34 . The imaging device according to  claim 33 , further comprising a first switching circuit, wherein a first pixel unit and a second pixel unit of the plurality of pixel units is configured to connect to the first comparator through the first switching circuit. 
     
     
         35 . The imaging device according to  claim 34 , further comprising a second switching circuit, wherein a third pixel unit and a fourth pixel unit of the plurality of pixel units is configured to connect to the third comparator through the second switching circuit.