Semiconductor memory device and method of manufacturing the same

Abstract

Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a memory transistor portion comprising:
 a source region of a second conductivity type, formed on a surface of a semiconductor substrate of a first conductivity type; 
 a tunnel drain region of the second conductivity type, formed apart from the source region; 
 a gate oxide film formed on the semiconductor substrate, partially comprising a tunnel insulating film and extending from a surface of the tunnel drain region to an edge of the source region; 
 a floating gate formed on the gate oxide film and 
 a control gate formed above the floating gate with an insulating film interposed between the floating gate and the control gate; and 
   a select transistor portion comprising:
 a fin-shaped first single-crystal semiconductor thin film of the first conductivity type, formed of the semiconductor substrate; 
 a drain region of the second conductivity type, formed on a surface of the fin-shaped first single-crystal semiconductor thin film; and 
 a select gate formed between the drain region and the tunnel drain region, above a upper surface and side surfaces of the fin-shaped first single-crystal semiconductor thin film with a select gate oxide film interposed between the select gate and the fin-shaped first single-crystal semiconductor thin film. 
   
     
     
         2 . A semiconductor memory device according to  claim 1 ,
 wherein a portion of the select gate that covers the upper surface of the fin-shaped single-crystal semiconductor thin film is extended in a direction of the drain region to form an overhang, and   wherein a region lower in concentration than the drain region is formed on a surface of the fin-shaped single-crystal semiconductor thin film under the overhang.   
     
     
         3 . A semiconductor memory device according to  claim 1 , further comprising an STI concave portion formed in the semiconductor substrate in order to dispose the select gate,
 wherein the STI concave portion has an STI internal oxide film embedded therein except for some regions,   wherein portions of the select gate that cover the side surfaces of the fin-shaped first single-crystal semiconductor thin film are formed in the some regions in which the STI internal oxide film is not embedded, and   wherein the STI internal oxide film and the select gate are spaced apart from each other in a channel length direction of the select transistor portion.   
     
     
         4 . A semiconductor memory device according to  claim 3 , further comprising a second drain region formed in a portion exposed by a separation of the select gate from the STI internal oxide film, adjacent to the select gate oxide film formed on side walls of the STI concave portion, the second drain region being formed to have a depth deeper than a depth of the drain region. 
     
     
         5 . A semiconductor memory device according to  claim 1 , wherein the select gate comprises a lower select gate and an upper select gate that is electrically connected to the lower select gate. 
     
     
         6 . A semiconductor memory device, comprising:
 a select transistor portion comprising:
 a fin-shaped first single-crystal semiconductor thin film formed of a semiconductor substrate of a first conductivity type; 
 a drain region of a second conductivity type formed on a surface of the fin-shaped first single-crystal semiconductor thin film; 
 a tunnel drain region of the second conductivity type formed on the surface of the fin-shaped first single-crystal semiconductor thin film apart from the drain region; and 
 a select gate formed between the drain region and the tunnel drain region, above a surface and side surfaces of the fin-shaped first single-crystal semiconductor thin film with a select gate oxide film interposed between the select gate and the fin-shaped first single-crystal semiconductor thin film; 
   a memory transistor portion comprising:
 a fin-shaped second single-crystal semiconductor thin film formed of the semiconductor substrate; 
 a source region of the second conductivity type formed on a surface of the fin-shaped second single-crystal semiconductor thin film; 
 a floating gate formed above the fin-shaped second single-crystal semiconductor thin film with a gate oxide film interposed between the fin-shaped second single-crystal semiconductor thin film and the floating gate, the gate oxide film extending from a surface of the tunnel drain region to an edge of the source region, the gate oxide film being formed on a upper surface and side surfaces of the fin-shaped second single-crystal semiconductor thin film and partially comprising a tunnel insulating film; and 
 a control gate formed above the floating gate with an insulating film interposed between the floating gate and the control gate. 
   
     
     
         7 . A semiconductor memory device according to  claim 6 ,
 wherein a portion of the select gate that covers the upper surface of the fin-shaped single-crystal semiconductor thin film is extended in a direction of the drain region to form an overhang, and   wherein a region lower in concentration than the drain region is formed on a surface of the fin-shaped single-crystal semiconductor thin film under the overhang.   
     
     
         8 . A semiconductor memory device according to  claim 6 , further comprising an STI concave portion formed in the semiconductor substrate in order to dispose the select gate,
 wherein the STI concave portion has an STI internal oxide film embedded therein except for some regions,   wherein portions of the select gate that cover the side surfaces of the fin-shaped first single-crystal semiconductor thin film are formed in the some regions in which the STI internal oxide film is not embedded, and   wherein the STI internal oxide film and the select gate are spaced apart from each other in a channel length direction of the select transistor portion.   
     
     
         9 . A semiconductor memory device according to  claim 8 , further comprising a second drain region formed in a portion exposed by a separation of the select gate from the STI internal oxide film, adjacent to the select gate oxide film formed on side walls of the STI concave portion, the second drain region being formed to have a depth deeper than a depth of the drain region. 
     
     
         10 . A semiconductor memory device according to  claim 6 ,
 wherein a portion of the floating gate, which covers the upper surface of the fin-shaped second single-crystal semiconductor thin film is extended in a channel length direction of the memory transistor portion to form an overhang, and   wherein a region lower in concentration than the drain region and the source region is formed in a surface layer of the fin-shaped second single-crystal semiconductor thin film that is under the overhang.   
     
     
         11 . A semiconductor memory device according to  claim 6 , wherein the select gate comprises a lower select gate and an upper select gate that is electrically connected to the lower select gate. 
     
     
         12 . A semiconductor memory device according to  claim 6 , further comprising an STI concave portion formed in the semiconductor substrate in order to dispose the floating gate,
 wherein the STI concave portion has an STI internal oxide film embedded therein except for some regions,   wherein portions of the floating gate that cover the side surfaces of the fin-shaped second single-crystal semiconductor thin film are formed in the some regions in which the STI internal oxide film is not embedded, and   wherein the STI internal oxide film and the floating gate are spaced apart from each other in a channel length direction in a vicinity of the source region of the memory transistor portion.   
     
     
         13 . A semiconductor memory device according to  claim 12 , further comprising a second source region formed in a portion exposed by a separation of the floating gate from the STI internal oxide film, adjacent to the gate oxide film formed on side walls of the STI concave portion, the second source region being formed to have a depth deeper than a depth of the source region. 
     
     
         14 . A method of manufacturing a semiconductor memory device,
 the semiconductor memory device comprising a memory transistor portion formed in a semiconductor substrate of a first conductivity type and a select transistor portion formed in a fin-shaped single-crystal semiconductor thin film of the first conductivity type, which is formed of the semiconductor substrate,   the method comprising:   forming, in a surface layer of the semiconductor substrate, a plurality of parallel low concentration impurity regions of a second conductivity type;   forming a plurality of parallel trenches that are orthogonal, in plan, to the plurality of parallel low concentration impurity regions;   embedding a first insulating film in the plurality of parallel trenches;   removing the first insulating film from a region for forming the select transistor portion to form STI concave portions and the fin-shaped single-crystal semiconductor thin film;   forming, in the region for forming the select transistor portion, a lower select gate above the fin-shaped single-crystal semiconductor thin film with a select gate oxide film interposed between the fin-shaped single-crystal semiconductor thin film and the lower select gate;   forming an upper select gate above the lower select gate with a second insulating film interposed between the lower select gate and the upper select gate;   forming, in a region for forming the memory transistor portion, a gate oxide film on the semiconductor substrate;   forming a tunnel insulating film in a part of the gate oxide film;   forming a floating gate on the gate oxide film;   forming a control gate above the floating gate with a third insulating film interposed between the floating gate and the control gate; and   forming a high concentration impurity region of the second conductivity type with the upper select gate and the control gate used as a mask.   
     
     
         15 . A method of manufacturing a semiconductor memory device,
 the semiconductor memory device comprising a memory transistor portion and a select transistor portion that are formed in a fin-shaped single-crystal semiconductor thin film of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type,   the method comprising:   forming, in a surface layer of the semiconductor substrate, a plurality of parallel low concentration impurity regions of a second conductivity type;   forming a plurality of parallel trenches that are orthogonal, in plan, to the plurality of parallel low concentration impurity regions;   embedding a first insulating film in the plurality of parallel trenches;   removing the first insulating film from a region for forming the memory transistor portion and a region for forming the select transistor portion to form STI concave portions and the fin-shaped single-crystal semiconductor thin film;   forming, in the region for forming the select transistor portion, a lower select gate above the fin-shaped single-crystal semiconductor thin film with a select gate oxide film interposed between the single-crystal semiconductor thin film and the lower select gate;   forming an upper select gate above the lower select gate with a second insulating film interposed between the lower select gate and the upper select gate;   forming, in the region for forming the memory transistor portion, a gate oxide film on the semiconductor substrate;   forming a tunnel insulating film in a part of the gate oxide film;   forming a floating gate on the gate oxide film;   forming a control gate above the floating gate with a third insulating film interposed between the floating gate and the control gate; and   forming a high concentration impurity region of the second conductivity type with the upper select gate and the control gate used as a mask.   
     
     
         16 . A method of manufacturing a semiconductor memory device according to  claim 14 ,
 wherein the forming of the lower select gate above the fin-shaped single-crystal semiconductor thin film, with the select gate oxide film interposed between the fin-shaped single-crystal semiconductor thin film and the lower select gate, and the forming of the floating gate on the gate oxide film are executed simultaneously, and   wherein the forming of the upper select gate above the lower select gate, with the second insulating film interposed between the lower select gate and the upper select gate, and the forming of the control gate above the floating gate, with the third insulating film interposed between the floating gate and the control gate, are executed simultaneously.   
     
     
         17 . A method of manufacturing a semiconductor memory device according to  claim 15 ,
 wherein the forming of the lower select gate above the fin-shaped single-crystal semiconductor thin film, with the select gate oxide film interposed between the fin-shaped single-crystal semiconductor thin film and the lower select gate, and the forming of the floating gate on the gate oxide film are executed simultaneously, and   wherein the forming of the upper select gate above the lower select gate, with the second insulating film interposed between the lower select gate and the upper select gate, and the forming of the control gate above the floating gate, with the third insulating film interposed between the floating gate and the control gate, are executed simultaneously.