Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate

Abstract

Electronic module ( 100 ), which comprises a first substrate ( 102 ), a first dielectric layer ( 104 ) on the first substrate ( 102 ), at least one electronic chip ( 106 ), which is mounted with a first main surface ( 108 ) directly or indirectly on partial region of the first dielectric layer ( 104 ), a second substrate ( 110 ) over a second main surface ( 114 ) of the at least one electronic chip ( 106 ), and an electrical contacting ( 116 ) for the electric contact of the at least one electronic chip ( 106 ) through the first dielectric layer ( 104 ), wherein the first adhesion layer ( 104 ) on the first substrate ( 102 ) extends over an area, which exceeds the first main surface ( 108 ).

1 . Electronic module, comprising:
 a first substrate;   a first dielectric layer on the first substrate;   at least an electronic chip, which is mounted with a first main surface directly or indirectly on a section of the first dielectric layer;   a second substrate over a second main surface of the at least one electronic chip;   an electrical contacting for electrically contacting the at least one electronic chip through the first dielectric layer;   wherein the first dielectric layer on the first substrate extends across an area, which exceeds the first main surface.   
     
     
         2 . Electronic module according to  claim 1 , comprising a second dielectric layer on the second substrate, wherein the at least one electronic chip is mounted with its second main surface directly or indirectly on a section of the second dielectric layer. 
     
     
         3 . Electronic module according to  claim 1 , wherein at least one of the first substrate and of the second substrate is a structured foil. 
     
     
         4 . Electronic module according to  claim 1 , wherein the first dielectric layer is formed of a full-surface layer with at least one through-hole, which is filled with an electrically conductive material, as electrical contact for electrically contacting the first main surface of the at least one electronic chip. 
     
     
         5 . Electronic module according to  claim 1 , comprising a plurality of electronic chips, wherein each of them is mounted with its first main surface on the first dielectric layer in such way, that a part of the first dielectric layer remains uncovered of the plurality of electronic chips. 
     
     
         6 . Electronic module according to  claim 1 , wherein the at least one electronic chip is configured as a power semiconductor chip. 
     
     
         7 . Electronic module according to  claim 2 , comprising a dielectric structure, in particular a laminate structure, to fill in particular completely at least one hollow space, which is delimited between the first dielectric layer, the second dielectric layer and the at least one electronic chip. 
     
     
         8 . Electronic module according to  claim 1 , wherein the first dielectric layer is formed by a first partial layer on the first substrate and a separate second partial layer on the first partial layer. 
     
     
         9 . Electronic module according to  claim 1 , comprising two electronic chips, wherein one of them has its active side on its first main surface and the other one has its active side on its second main surface. 
     
     
         10 . Electronic module according to claim, comprising a plurality of electronic chips, which are electrically coupled with each other on at least one of the first main surface and the second main surface by the electrical contacting. 
     
     
         11 . Electronic module according to  claim 1 , comprising at least one through hole filled with electrically conductive material, which extends perpendicular to the first substrate and the second substrate to form an electrical coupling of the first substrate with the second substrate. 
     
     
         12 . Method of manufacturing at least one electronic module, wherein the method comprises:
 applying a first adhesion layer at least to an entire component mounting area of a first substrate;   direct or indirect mounting of a first main surface of at least one electronic chip on a partial region of the first adhesion layer;   arranging a second substrate over a second main surface of the at least one electronic chip;   electrical contacting of the at least one electronic chip through the first adhesion layer.   
     
     
         13 . Method according to  claim 12 , further comprising:
 applying a second adhesion layer on a second substrate;   direct or indirect mounting of the second main surface of at least one electronic chip on a section of the second adhesion layer.   
     
     
         14 . Method according to  claim 13 , wherein the second adhesion layer is applied at least to an entire component mounting area of the second substrate. 
     
     
         15 . Method according to  claim 13 , wherein at least one of the first adhesion layer and of the second adhesion layer is applied essentially completely on the respective substrate. 
     
     
         16 . Method according to  claims 13 , wherein at least one through hole for electrically contacting the respective main surface of the respective electronic chip ( 106 ) is formed in at least one of the first adhesion layer ( 104 ) and of the second adhesion layer ( 112 ). 
     
     
         17 . Method according to  claim 16 , wherein the at least one through hole for electrically contacting the respective main surface of the respective electronic chip is filled at least partially with electrically conductive material. 
     
     
         18 . Method according to  claim 13 , wherein at least one of the first adhesion layer and of the second adhesion layer is mounted in a two-phase process on the respective substrate ( 102 ,  110 ), wherein at first in a first phase, a first partial layer is mounted on the respective substrate, and then in a separate and subsequent second phase, a second partial layer is mounted on the first partial layer. 
     
     
         19 . Method according to  claim 12 , wherein at least one of the first substrate and of the second substrate is structured, in particular by etching, to thus form electrically conductive paths. 
     
     
         20 . Method according to  claim 12 , comprising a singularizing of a plurality of electronic chips between the first substrate and the first adhesion layer, on the one hand, and the second substrate, on the other hand, to a plurality of electronic modules, wherein each of them comprises at least a section of the first substrate, a section of the first adhesion layer, a section of the second substrate and at least one electronic chip. 
     
     
         21 . Method for manufacturing at least one electronic module, wherein the method comprises:
 applying a first adhesion layer at least to an entire component mounting area of a first substrate;   direct or indirect mounting a first main surface of a plurality of electronic chips on a respective partial region of the first adhesion layer;   arranging a second adhesion layer on a second substrate;   direct or indirect mounting a second main surface of a plurality of electronic chips on a respective partial region of the second adhesion layer.   
     
     
         22 . Method according to  claim 21 , wherein the second adhesion layer is applied at least to an entire component mounting area of the second substrate. 
     
     
         23 . Method according to  claim 21 , wherein at least one of the first adhesion layer and of the second adhesion layer is applied essentially completely on the respective substrate. 
     
     
         24 . Method according to  claim 21 , wherein at least one through hole for electrically contacting the respective main surface of the respective electronic chip ( 106 ) is formed in at least one of the first adhesion layer ( 104 ) and of the second adhesion layer ( 112 ). 
     
     
         25 . Method according to  claim 24 , wherein the at least one through hole for electrically contacting the respective main surface of the respective electronic chip is filled at least partially with electrically conductive material. 
     
     
         26 . Method according to  claim 21 , wherein at least one of the first adhesion layer and of the second adhesion layer is mounted in a two-phase process on the respective substrate ( 102 ,  110 ), wherein at first in a first phase, a first partial layer is mounted on the respective substrate, and then in a separate and subsequent second phase, a second partial layer is mounted on the first partial layer. 
     
     
         27 . Method according to  claim 21 , wherein at least one of the first substrate and of the second substrate is structured, in particular by etching, to thus form electrically conductive paths. 
     
     
         28 . Method according to  claim 21 , comprising a singularizing of a plurality of electronic chips between the first substrate and the first adhesion layer, on the one hand, and the second substrate, on the other hand, to a plurality of electronic modules, wherein each of them comprises at least a section of the first substrate, a section of the first adhesion layer, a section of the second substrate and at least one electronic chip.