Data sensing circuit and semiconductor apparatus using the same

Abstract

A data sensing circuit may include a pair of first signal lines, and a pair of second signal lines precharged with a first power supply voltage. The data sensing circuit may also include a line level control block configured for applying a second power supply voltage to any one signal line of the pair of second signal lines in response to a read command.

What is claimed is: 
     
         1 . A data sensing circuit comprising:
 a pair of first signal lines;   a pair of second signal lines configured to be precharged with a first power supply voltage; and   a line level control block configured to apply a second power supply voltage to any one signal line of the pair of second signal lines in response to a read command.   
     
     
         2 . The data sensing circuit according to  claim 1 , further comprising:
 a first signal sensing block coupled between the pair of first signal lines and the pair of second signal lines, and configured to supply a ground voltage to the other of the pair of second signal lines in response to the read command.   
     
     
         3 . The data sensing circuit according to  claim 1 , wherein the line level control block is configured to apply the second power supply voltage to any one of the pair of second signal lines after a predetermined time passes after inputting the read command. 
     
     
         4 . The data sensing circuit according to  claim 1 , wherein the line level control block comprises:
 a latch unit configured to supply the second power supply voltage to any one of the pair of second signal lines in response to a line level control signal; and   a signal generation logic configured to generate the line level control signal which is activated after the predetermined time passes after the read command and is deactivated before receiving a precharge command.   
     
     
         5 . The data sensing circuit according to  claim 4 , wherein the latch unit comprises a semi-latch including any one of a PMOS cross-coupled latch and an NMOS cross-coupled latch. 
     
     
         6 . A semiconductor apparatus comprising:
 a plurality of memory blocks respectively including one of a plurality of first signal sensing blocks which are coupled to a plurality of memory cell arrays through a plurality of pairs of first signal lines;   a plurality of pairs of second signal lines coupled to the first signal sensing blocks and precharged to a voltage level of a first power supply voltage level; and   a plurality of line level control blocks coupled to the plurality of pairs of second signal lines,   wherein, among the first signal sensing blocks and the plurality of line level control blocks, a first signal sensing block and a line level control block corresponding to a memory block which is activated among the plurality of memory blocks are configured to sense data of a pair of first signal lines of the activated memory block.   
     
     
         7 . The semiconductor apparatus according to  claim 6 , further comprising:
 a control signal generation block configured to create a plurality of sets of control signals which have activation information of the activated memory block, in response to an address signal and a command.   
     
     
         8 . The semiconductor apparatus according to  claim 7 , wherein the plurality of sets of control signals comprise:
 a set of first control signals configured for controlling selective precharge of the plurality of pairs of second signal lines; and   a set of second control signals configured for controlling selective activation of the first signal sensing blocks.   
     
     
         9 . The semiconductor apparatus according to  claim 8 , wherein the plurality of sets of control signals further comprise:
 a set of third control signals configured for controlling electrical coupling/decoupling of the plurality of pairs of first signal lines and the plurality of pairs of second signal lines.   
     
     
         10 . The semiconductor apparatus according to  claim 8 , further comprising:
 an equalize block configured to equalize the plurality of pairs of second signal lines in response to the set of first control signals.   
     
     
         11 . The semiconductor apparatus according to  claim 6 , further comprising:
 a second signal sensing block coupled to the plurality of pairs of second signal lines; and   a data input/output block coupled to the second signal sensing block through a plurality of third signal lines.   
     
     
         12 . The semiconductor apparatus according to  claim 11 , wherein the data input/output block comprises a plurality of input/output pads. 
     
     
         13 . The semiconductor apparatus according to  claim 8 , wherein the line level control block, corresponding to a memory block which is activated among the plurality of memory blocks, is configured to apply a second power supply voltage to any one signal line of a pair of second signal lines which are coupled therewith, in response to control signals corresponding to the activated memory block among the set of first control signals and the set of second control signals. 
     
     
         14 . The semiconductor apparatus according to  claim 13 , wherein the first signal sensing block, corresponding to a memory block which is activated among the plurality of memory blocks, is configured to apply a ground voltage to the other signal line of a pair of second signal lines which are coupled therewith, in response to a control signal corresponding to the activated memory block among the set of second control signals. 
     
     
         15 . The semiconductor apparatus according to  claim 13 , wherein the line level control block is configured to apply the second power supply voltage to any one signal line of the pair of second signal lines which are coupled therewith, after a predetermined time passes after an activation time of any one of control signals corresponding to the activated memory block. 
     
     
         16 . The semiconductor apparatus according to  claim 6 , wherein the line level control block comprises:
 a latch unit configured to apply the second power supply voltage to any one signal line of the pair of second signal lines which are coupled therewith, in response to a line level control signal; and   a signal generation logic configured to generate the line level control signal which is activated after the predetermined time passes after a read command and is deactivated prior to receiving a precharge command.   
     
     
         17 . The semiconductor apparatus according to  claim 8 , wherein the line level control block comprises:
 a latch unit configured to apply the second power supply voltage to any one signal line of the pair of second signal lines which are coupled therewith, in response to a line level control signal; and   a signal generation logic configured to generate the line level control signal in response to the set of first control signals and the set of second control signals.   
     
     
         18 . The semiconductor apparatus according to  claim 17 , wherein the latch unit comprises a semi-latch including any one of a PMOS cross-coupled latch and an NMOS cross-coupled latch.