Semiconductor device and communication interface circuit

Abstract

A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

1 - 9 . (canceled) 
     
     
         10 . A semiconductor device, comprising:
 an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded,   wherein a source or drain of a first-stage first conductivity type MOS transistor among the cascaded first conductivity type MOS transistors is used as a first terminal,   wherein a source or drain of a last-stage first conductivity type MOS transistor among the cascaded first conductivity type MOS transistors is used as a second terminal,   wherein the respective gates of the cascaded first conductivity type MOS transistors receive a control signal for controlling an opening or short-circuiting between the first and second terminals,   wherein said first and second terminals are coupled to respective first and second differential signal lines each connected to a respective one of a pair of input/output terminals of a host,   wherein said semiconductor device further comprises a first single-ended receiver constructed to output a first signal based on whether or not a voltage present at said first differential signal line exceeds a threshold voltage and a second single-ended receiver constructed to output a second signal based on whether or not a voltage present at said second differential signal line exceeds said threshold voltage, and   wherein said host is configured to determine that a device has been coupled to said pair of input/output terminals of the host based on said first and second signals having different states.   
     
     
         11 . The semiconductor device according to  claim 10 , further comprising:
 a first resistor, one end of which is coupled to the source or drain of the first-stage first conductivity type MOS transistor and other end of which is used as the first terminal; and   a second resistor, one end of which is coupled to the source or drain of the last-stage first conductivity type MOS transistor and other end of which is used as the second terminal.   
     
     
         12 . The semiconductor device according to  claim 11 ,
 wherein backgates of the first conductivity type MOS transistors included in the interterminal opening/closing section are mutually coupled.   
     
     
         13 . A semiconductor device comprising:
 a first P-channel type MOS transistor, a source or drain of which is used as a first terminal; and   a second P-channel type MOS transistor, a source or drain of which is coupled to the source or drain different from the first terminal and other source or drain of which is used as a second terminal,   wherein gates of the first and second P-channel type MOS transistors receive a control signal for controlling an opening or short-circuiting between the first and second terminals,   wherein said first and second terminals are coupled to respective first and second differential signal lines each connected to a respective one of a pair of input/output terminals of a host,   wherein said semiconductor device further comprises a first single-ended receiver constructed to output a first signal based on whether or not a voltage present at said first differential signal line exceeds a threshold voltage, and a second single-ended receiver constructed to output a second signal based on whether or not a voltage present at said second differential signal line exceeds said threshold voltage, and   wherein said host is configured to determine that a device has been coupled to said pair of input/output terminals of the host based on said first and second signals having different states.   
     
     
         14 . A communication interface circuit comprising:
 an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded,   wherein a source or drain of a first-stage first conductivity type MOS transistor among the cascaded first conductivity type MOS transistors is used as a first terminal,   wherein a source or drain of a last-stage first conductivity type MOS transistor among the cascaded first conductivity type MOS transistors is used as a second terminal,   wherein the respective gates of the cascaded first conductivity type MOS transistors receive a control signal for controlling an opening or short-circuiting between the first and second terminals,   wherein the first terminal is coupled to a terminal for receiving one of a pair of differential signals,   wherein the second terminal is coupled to a terminal for receiving the other of a pair of differential signals,   wherein said first and second terminals and said pair of differential signal lines are connected to a pair of input/output terminals of a host,   wherein said communication interface circuit further comprises a first single-ended receiver constructed to output a first signal based on whether or not a voltage present at said first differential signal line exceeds a threshold voltage, and a second single-ended receiver constructed to output a second signal based on whether or not a voltage present at said second differential signal line exceeds said threshold voltage, and   wherein said host is configured to determine that a device has been coupled to said pair of input/output terminals of the host based on said first and second signals having different states.   
     
     
         15 . The communication interface circuit according to  claim 14 , wherein the communication interface circuit complies with USB (Universal Serial Bus) specifications for transmitting/receiving data. 
     
     
         16 . The semiconductor device according to  claim 10 , wherein each said first-stage first conductivity type MOS transistor is a first conductivity type-only MOS transistor. 
     
     
         17 . The communication interface circuit according to  claim 14 , wherein each said first-stage first conductivity type MOS transistor is a first conductivity type-only MOS transistor.