Transactional memory that is programmable to output an alert if a predetermined memory write occurs

Abstract

A transactional memory receives a command, where the command includes an address and a novel GAA (Generate Alert On Action) bit. If the GAA bit is set and if the transactional memory is enabled to generate alerts and if the command is a write into a memory of the transactional memory, then the transactional memory outputs an alert in accordance with preconfigured parameters. For example, the alert may be preconfigured to carry a value or key usable by the recipient of the alert to determine the reason for the alert. The alert may be set up to include the address of the memory location in the transactional memory that was written. The transactional memory may be set up to send the alert to a predetermined destination. The outputting of the alert may be a writing of information into a predetermined destination, or may be an outputting of an interrupt signal.

What is claimed is: 
     
         1 . A transactional memory, comprising:
 a memory; and   an interface circuit that receives a command onto the transactional memory, wherein the command includes an incoming address and a “Generate Alert On Action” (GAA) bit, wherein if the command is a command to write into the memory and the GAA bit is set then the interface circuit outputs an alert from the transactional memory.   
     
     
         2 . The transactional memory of  claim 1 , wherein the transactional memory comprises a write alert enable/disable bit, wherein if the write alert enable/disable bit stores a first digital logic value then the interface circuit is enabled to output the alert provided that the GAA bit is set, whereas if the write alert enable/disable bit stores a second digital logic value then the interface circuit is disabled from outputting the alert. 
     
     
         3 . The transactional memory of  claim 1 , wherein the interface circuit outputs the alert by writing information to a predetermined destination. 
     
     
         4 . The transactional memory of  claim 1 , wherein the interface circuit stores an event value, and wherein the event value is output from the transactional memory as part of the alert. 
     
     
         5 . The transactional memory of  claim 1 , wherein the alert includes the address of a memory location of the memory that was written as a result of the command. 
     
     
         6 . The transactional memory of  claim 1 , wherein the interface circuit comprises:
 a pipeline that reads from and writes to the memory, wherein the pipeline receives and processes operation codes;   an autopush circuit that is preconfigured to inject an operation code into the pipeline if a writing into the memory occurs when the GAA bit is set, and wherein the injected operation code causes the pipeline to output the alert from the transactional memory; and   interface FIFO (First In First Out) memories that interface the pipeline to a bus.   
     
     
         7 . The transactional memory of  claim 1 , wherein the interface circuit is preconfigured to store an address of a destination, and wherein the outputting of the alert from the transactional memory involves using the address to send the alert to the destination. 
     
     
         8 . The transactional memory of  claim 1 , wherein the interface circuit outputs the alert by outputting of an interrupt signal. 
     
     
         9 . A method comprising:
 (a) receiving a command onto a transactional memory, wherein the command includes a “Generate Alert On Action” (GAA) bit; and   (b) if the GAA bit is set and the transactional memory is enabled to output a write alert and if the command is a command to write to a memory of the transactional memory then the transactional memory outputs an alert, otherwise if either the GAA bit is not set or if the transactional memory is not enabled to output a write alert or if the command is not a command to write to the memory then the transactional memory does not output an alert, wherein (a) and (b) are performed by the transactional memory.   
     
     
         10 . The method of  claim 9 , wherein the alert is output in (b) by writing information to a predetermined destination. 
     
     
         11 . The method of  claim 9 , further comprising:
 (c) storing on the transactional memory an address of a destination, and wherein the alert is output in (b) by using the address to send the alert to the destination.   
     
     
         12 . The method of  claim 9 , further comprising:
 (c) storing on the transactional memory an event value, and wherein the event value is output from the transactional memory as part of the alert.   
     
     
         13 . The method of  claim 9 , wherein the alert that is output in (b) is an interrupt signal that is output from the transactional memory. 
     
     
         14 . The method of  claim 9 , further comprising:
 (c) writing configuration information from a processor and into the transactional memory, wherein the configuration information includes address information of a destination, and wherein the transactional memory then uses the address information to write the alert into the destination; and   (d) receiving the alert into the destination, wherein the processor then reads the alert from the destination.   
     
     
         15 . A transactional memory, comprising:
 a memory; and   means for receiving a command onto the transactional memory, wherein the command includes a “Generate Alert On Action” (GAA) bit, wherein the means is also for outputting an alert from the transactional memory if the command is a command to write into the memory and the GAA bit is set.   
     
     
         16 . The transactional memory of  claim 15 , wherein the means includes a write alert enable/disable bit, wherein if the write alert enable/disable bit stores a first digital logic value then the means is enabled to output the alert provided that the GAA bit is set and provided that the command caused a write to the memory, whereas if the write alert enable/disable bit stores a second digital logic value then the means is disabled from outputting the alert. 
     
     
         17 . The transactional memory of  claim 15 , wherein the means comprises:
 a pipeline that reads from and writes to the memory, wherein the pipeline processes operation codes;   an autopush circuit that is preconfigured to inject an operation code into the pipeline if a writing into the memory occurs when the GAA bit is set, and wherein the injected operation code causes the pipeline to output the alert from the transactional memory; and   interface FIFO (First In First Out) memories that interface the pipeline to a bus.   
     
     
         18 . The transactional memory of  claim 17 , wherein the command is received onto the transactional memory from the bus, and wherein the alert is output from the transactional memory onto the bus. 
     
     
         19 . The transactional memory of  claim 15 , wherein the means is also for storing an event value, wherein the means is also for including the event value as part of the alert that is output from the transactional memory. 
     
     
         20 . The transactional memory of  claim 15 , wherein the command results in a write into a memory location of the memory, wherein the means is also for including an address of the memory location as part of the alert that is output from the transactional memory.