Semiconductor device and control method thereof

Abstract

Provided is a semiconductor device including: a first memory that stores multiple instructions; a second memory that stores multiple data items; first and second buses; a microprocessor that fetches, through the first bus, an instruction at a specified address among the multiple instructions stored in the first memory, executes the instruction, and accesses the second memory through the second bus based on a result of the execution; and a trace information output unit that acquires, when a branch instruction is generated in the microprocessor, address information of the first memory specified before branching, and outputs the information as trace information. The trace information output from the trace information output unit is written into the second memory through the second bus in a period in which the microprocessor does not access the second memory during execution of the branch instruction.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a processor that has a pipeline and executes a plurality of instructions using the pipeline;   a trace unit that outputs a trace information of the processor; and   a memory that stores both execution results of the instructions by the processor and the trace information,   wherein when the processor executes a branch instruction, the trace unit outputs the trace information to the memory.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the memory stores the execution results of the instructions when the processor executes the instructions other than the branch instruction and stores the trace information when the processor executes the branch instruction. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the trace unit outputs the trace information when the processor executes an instruction after the execution of the branch instruction. 
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein the pipeline includes a fetch stage, a decode stage and a memory access stage, and   wherein the trace unit outputs the trace information to the memory when the memory access stage is empty.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein the memory sores the trace information during the memory access stage. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the trace unit outputs an address information of the branch instruction as the trace information. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the branch instruction includes a subroutine call instruction.