Identification and mitigation of hard errors in memory systems

Abstract

Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.

What is claimed is: 
     
         1 . A method for detecting a fault in a multi-level memory cell in a memory, wherein the multi-level memory cell is configured to store at least a first bit and a second bit, the method comprising:
 decoding the first bit of the multi-level memory cell by correcting a first value of the first bit to a second value, wherein the second value corresponds to N number of threshold voltage ranges of the multi-level memory cell; and
 in response to failing to decode the second bit of the multi-level memory cell, 
 identifying a first threshold voltage range associated with the second bit of the multi-level memory cell, 
 determining whether the first threshold voltage range is adjacent to, or included in at least one of the N number of threshold voltage ranges, and 
 In response to the first threshold range being neither adjacent to, nor included in, at least one of the N number of threshold voltage ranges, identifying the multi-level memory cell as potentially having a fault. 
   
     
     
         2 . The method of  claim 1 , further comprising:
 In response to the first threshold range being neither adjacent to, nor included in, at least one of the N number of threshold voltage ranges, (i) assigning a log-likelihood ratio (LLR) of zero to the second bit of the multi-level memory cell, and (ii) attempting to re-decode the second bit of the multi-level memory cell based on the LLR of zero assigned to the second bit of the multi-level memory cell.   
     
     
         3 . The method of  claim 1 , wherein identifying the multi-level memory cell as having the fault comprises:
 identifying the multi-level memory cell as a potential stuck cell.   
     
     
         4 . The method of  claim 1 , further comprising:
 in response to identifying the multi-level memory cell as potentially having a fault, determining that the first bit and the second bit are stuck to a third value and a fourth value, respectively, irrespective of how the first bit and the second bit are being programmed.   
     
     
         5 . The method of  claim 1 , wherein the first threshold voltage range includes a threshold voltage to which the multi-level memory cell is actually programmed. 
     
     
         6 . The method of  claim 1 , wherein the N number of threshold voltage ranges includes a threshold voltage to which the multi-level memory cell was intended to be programmed. 
     
     
         7 . The method of  claim 1 , wherein:
 the first bit is a maximum distance (MD) bit of the multi-level memory cell.   
     
     
         8 . The method of  claim 7 , wherein:
 the second bit is a least distance (LD) bit of the multi-level memory cell   
     
     
         9 . The method of  claim 1 , wherein identifying the first threshold voltage range associated with the second bit of the multi-level memory cell further comprises:
 based on (i) the read data associated with the first bit and (ii) the read data associated with the second bit, identifying the first threshold voltage range associated with the second bit of the multi-level memory cell.   
     
     
         10 . The method of  claim 1 , wherein the memory is one of an electrically-erasable programmable read-only memory (EEPROM) and a flash memory. 
     
     
         11 . A memory system comprising:
 a memory comprising a multi-level memory cell, wherein the multi-level memory cell is configured to store at least a first bit and a second bit;   a decoder module configured to decode the first bit of the multi-level memory cell by correcting a first value of the first bit to a second value, wherein the second value corresponds to N number of threshold voltage ranges of the multi-level memory cell; and   a read control module configured to, in response to the decoder module failing to decode the second bit,
 identify a first threshold voltage range associated with the second bit, and 
 determine whether the first threshold voltage range is adjacent to, or included in at least one of the N number of threshold voltage ranges, 
   wherein in response to the first threshold range being neither adjacent to, nor included in, at least one of the N number of threshold voltage ranges, the multi-level memory cell is identified as potentially having a fault.   
     
     
         12 . The memory system of  claim 11 , further comprising:
 an log-likelihood ratio (LLR) estimation module configured to, in response to the first threshold range being neither adjacent to, nor included in, at least one of the N number of threshold voltage ranges, assign a log-likelihood ratio (LLR) of zero to the second bit of the multi-level memory cell,   wherein the decoder module is further configured to attempt to re-decode the second bit of the multi-level memory cell based on the LLR of zero assigned to the second bit of the multi-level memory cell.   
     
     
         13 . The memory system of  claim 11 , wherein the multi-level memory cell is identified as potentially having the fault by identifying the multi-level memory cell as being a potential stuck cell. 
     
     
         14 . The memory system of  claim 11 , wherein:
 in response to the multi-level memory cell being identified as potentially having the fault, the first bit and the second bit are determined to be stuck to a third value and a fourth value, respectively, irrespective of how the first bit and the second bit are being programmed.   
     
     
         15 . The memory system of  claim 11 , wherein the first threshold voltage range includes a threshold voltage to which the multi-level memory cell is actually programmed. 
     
     
         16 . The memory system of  claim 11 , wherein the N number of threshold voltage ranges includes a threshold voltage to which the multi-level memory cell was intended to be programmed. 
     
     
         17 . The memory system of  claim 11 , wherein:
 the first bit is a maximum distance (MD) bit of the multi-level memory cell; and   the second bit is a least distance (LD) bit of the multi-level memory cell   
     
     
         18 . The memory system of  claim 11 , wherein the memory is one of an electrically-erasable programmable read-only memory (EEPROM) and a flash memory. 
     
     
         19 . A method for operating a memory comprising a plurality of word lines, wherein each of the plurality of word lines comprises M number of memory cells, wherein M is an integer, wherein the memory further comprises M number of bit lines, wherein each of the M number of bit lines is associated with a corresponding memory cell of the M number of memory cells in each of the plurality of word lines, and wherein the method comprises:
 while decoding read data from each of a subset of the plurality of word lines, identifying that for each of at least a first number of word lines, a K th  memory cell of the M number of memory cells has an error; and   in response to the first number being greater than a threshold, determining that the K th  bit line of the M number of bit lines is faulty.   
     
     
         20 . The method of  claim 19 , further comprising:
 in response to determining that the K th  bit line is faulty, assigning, for each of the plurality of word lines, a log-likelihood ratio (LLR) of zero to the K th  memory cell of the M number of memory cells of the corresponding word line;   re-decoding read data from one or more of the plurality of word lines using the assigned LLR of zero; and   in response to determining that the K th  bit line is faulty, marking, for each of the plurality of word lines, the K th  memory cell of the M number of memory cells for erasure.