Replacement metal gate including dielectric gate material

Abstract

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, the method comprising:
 forming at least one semiconductor fin on a semiconductor substrate;   forming an etch stop layer on an upper surface of the at least one semiconductor fin;   forming a plurality of gate formation layers on the etch stop layer and the substrate, the plurality of gate formation layers including a dummy gate layer formed from a dielectric material;   patterning the plurality of gate formation layers to form a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from the dielectric material;   depositing a spacer layer that conforms with an outer surface of each dummy gate element; and   etching the spacer layer to form a spacer on each sidewall of the dummy gate elements and etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fin.   
     
     
         2 . The method of  claim 1 , further comprising epitaxially growing a semiconductor material from the exposed portion of the semiconductor fin after etching the spacer layer and the portion of the etch stop layer. 
     
     
         3 . The method of  claim 2 , wherein the dummy gate element is formed from a material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (SiO 2 ), and a silicon boron carbide material that contains nitrogen (SiB:C(N)). 
     
     
         4 . The method of  claim 3 , wherein the patterning the plurality of gate formation layers includes patterning a photoresist layer to form a plurality of photoresist elements at a top surface of the plurality of gate formation layers. 
     
     
         5 . The method of  claim 4 , wherein the patterning the plurality of gate formation layers further includes patterning a gate hardmask layer formed on an upper surface of the dummy gate layer according to the plurality of photoresist elements to form a plurality of respective gate caps on the dummy gate layer. 
     
     
         6 . The method of  claim 5 , wherein the patterning the plurality of gate formation layers further includes patterning the dummy gate layer according to the plurality of gate caps to form the plurality of dummy gate elements. 
     
     
         7 . The method of  claim 6 , wherein the patterning the plurality of gate formation layers is performed according to a trilayer resist patterning scheme. 
     
     
         8 . A method of fabricating a semiconductor device, the method comprising:
 forming at least one semiconductor fin on a semiconductor substrate;   forming an etch stop layer on an upper surface of the at least one semiconductor fin;   patterning a photoresist layer to form a plurality of photoresist elements above a dummy gate layer that is formed from a dielectric material;   patterning the dummy gate layer using the plurality of photoresist elements to form plurality of respective dummy gate elements on the etch stop layer, each dummy gate element formed from the dielectric material;   depositing a spacer layer that conforms to an outer surface of each dummy gate element;   etching the spacer layer to form a spacer on each sidewall of the dummy gate elements; and   etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fins.   
     
     
         9 . The method of  claim 8 , wherein the etching a portion of the etch stop layer includes performing a pre-clean process after etching the spacer layer, the pre-clean process forming cavities in the etch stop layer located between the dummy gate elements to expose an underlying portion of the at least one semiconductor fin. 
     
     
         10 . The method of  claim 9 , further comprising epitaxially growing semiconductor material from the cavities such that a portion of the epitaxially grown semiconductor material contacts a pair of opposing spacers to form a source/drain region. 
     
     
         11 . The method of  claim 10 , further comprising depositing a contact dielectric layer that fills a void between the spacers and covers an upper portion of the dummy gate elements. 
     
     
         12 . The method of  claim 11 , further comprising performing a planarization process that partially recesses the contact dielectric layer and stops on the dummy gate elements such that an upper portion of the dummy gate elements is flush with the contact dielectric layer. 
     
     
         13 . The method of  claim 12 , further comprising removing the dummy gate elements to form respective trenches between a pair of respective spacers. 
     
     
         14 . The method of  claim 13 , further comprising filling each trench with a metal gate material to form a respective metal gate element. 
     
     
         15 . The method of  claim 14 , further comprising a plurality of gate formation layers formed on an upper surface of the dummy gate layer, the plurality of gate formation layers including a hardmask layer formed on a gate hardmask layer formed on an upper surface of the dummy gate layer, and an organic layer interposed between the hardmask layer and the photoresist layer. 
     
     
         16 . A method of fabricating a semiconductor device, the method comprising:
 forming at least one semiconductor fin on a semiconductor substrate;   forming an etch stop layer on an upper surface of the at least one semiconductor fin;   forming a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from a dielectric material and having a hardmask gate cap formed on an upper surface of the semiconductor fin;   depositing a high-dielectric constant layer that conforms to an outer surface of each dummy gate element and depositing a spacer layer on the high-dielectric constant layer;   performing a first etching process that etches the spacer layer to form a spacer on each sidewall of dummy gate elements and exposes an upper portion of the high-dielectric constant layer;   performing a second etching process different from the first etching process that selectively etches the upper portion of the high-dielectric constant layer to expose each hardmask gate cap;   removing the hardmask gate caps and the dummy gate elements to form a trench between a respective pair of spacers; and   performing a third etching process after removing the dummy gates elements to remove a portion of the high-dielectric constant material from the sidewalls of the spacers such that a remaining portion of the high-dielectric constant material is interposed between the spacers and the etch stop layer.   
     
     
         17 . The method of  claim 16 , further comprising performing a planarization process before removing the dummy gate elements to recess the hardmask gate cap such that an upper portion of the dummy gate elements is exposed. 
     
     
         18 . The method of  claim 17 , wherein the dummy gate element is formed from a material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (SiO 2 ), and a silicon boron carbide material that contains nitrogen (SiB:C(N)). 
     
     
         19 . The method of  claim 18 , further comprising depositing a gate material in the trenches to form a metal gate element that contacts the spacers, the remaining portion of high-dielectric constant material and the etch stop layer. 
     
     
         20 . The method of  claim 19 , wherein the first etching process is a reactive ion etching process, the second etching process is a carina etching process, and the third etching process is a carina etching process.