Engineering multiple threshold voltages in an integrated circuit

Abstract

An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors.

We claim: 
     
         1 . An integrated circuit comprising:
 a first field-effect transistor having a gate stack comprising a first electrically insulating material that is ferroelectric and a first level of strain, S 1 , being induced in the first field-effect transistor gate stack by an element exterior to the first field-effect transistor, the first field-effect transistor having a first threshold voltage, Vt 1 ;   a second field-effect transistor having a gate stack comprising a second electrically insulating material that is ferroelectric and a second level of strain, S 2 , being induced in the second field-effect transistor gate stack by an element exterior to the second field-effect transistor, the second field-effect transistor having a second threshold voltage, Vt 2 ; and   a third field-effect transistor having a gate stack comprising a third electrically insulating material that is different from the first and second electrically insulating materials and a third level of strain, S 3 , the third field-effect transistor having a third threshold voltage, Vt 3 , wherein the third level of strain, S 3 , being induced in the third field-effect transistor gate stack;   wherein the first and second electrically insulating materials are the same electrically insulating material and wherein the first and second electrically insulating materials and the first, second, and third levels of strain S 1 , S 2 , and S 3 , are configured to shift at least one of the first, second, and third threshold voltages Vt 1 , Vt 2 , and Vt 3  relative to each other by a predetermined amount such that Vt 1 , Vt 2 , and Vt 3  are all set to different predetermined values, wherein S 1 , S 2  and S 3  are all greater than zero.   
     
     
         2 . The integrated circuit of  claim 1  wherein the gate stack in the third field-effect transistor does not comprise an electrically insulating material that is ferroelectric in the third field-effect transistor or can become ferroelectric in the third field-effect transistor when strain is induced in the gate stack. 
     
     
         3 . The integrated circuit of  claim 1  wherein the gate stack in the third field-effect transistor comprises an electrically insulating material that is ferroelectric in the third field-effect transistor or can become ferroelectric in the third field-effect transistor when strain is induced in the gate stack. 
     
     
         4 . The integrated circuit of  claim 1  wherein the gate stack in the third field-effect transistor comprises an electrically insulating material that is ferroelectric in the third field-effect transistor only when strain is induced in the gate stack. 
     
     
         5 . The integrated circuit of  claim 1  wherein the strain induced in the gate stacks of the first, second and third field-effect transistors is substantially uniaxial process-induced strain. 
     
     
         6 . The integrated circuit of  claim 1  wherein the ferroelectric material is selected from the group consisting of BaTiO 3 , Pb[Zr x Ti 1-x ]O 3  (PZT), SrBi 2 Ta 2 O 9  (SBT), SrTiO 3  (STO), Ba 1-x Sr x TiO 3  (BST), PbTiO 3 , EuTiO 3 , CaMnO 3  and BiFeO 3 . 
     
     
         7 . An integrated circuit comprising:
 a first field-effect transistor having a gate stack comprising a first electrically insulating material that is ferroelectric and a first level of strain, S 1 , being induced in the first field-effect transistor gate stack by an element exterior to the first field-effect transistor, the first field-effect transistor having a first threshold voltage, Vt 1 ;   a second field-effect transistor having a gate stack comprising a second electrically insulating material that is ferroelectric and a second level of strain, S 2 , being induced in the second field-effect transistor gate stack by an element exterior to the second field-effect transistor, the second field-effect transistor having a second threshold voltage, Vt 2 ; and   a third field-effect transistor having a gate stack comprising a third electrically insulating material that is ferroelectric and a third level of strain, S 3 , the third field-effect transistor having a third threshold voltage, Vt 3 , wherein the third level of strain, S 3 , being induced in the third field-effect transistor gate stack;   wherein the first and second electrically insulating materials are the same electrically insulating material and wherein the first and second electrically insulating materials and the first, second, and third levels of strain S 1 , S 2 , and S 3 , are configured to shift at least one of the first, second, and third threshold voltages Vt 1 , Vt 2 , and Vt 3  relative to each other by a predetermined amount such that Vt 1 , Vt 2 , and Vt 3  are all set to different predetermined values, wherein S 1 , S 2  and S 3  are all greater than zero.   
     
     
         8 . The integrated circuit of  claim 7  wherein the gate stack in the third field-effect transistor comprises a third ferroelectric material that is the same as the first and second ferroelectric materials wherein S 1  is greater than S 2  which is greater than S 3 . 
     
     
         9 . The integrated circuit of  claim 7  wherein the strain induced in the gate stacks of the first, second and third field-effect transistors is substantially uniaxial process-induced strain. 
     
     
         10 . The integrated circuit of  claim 7  wherein the ferroelectric in the third field-effect transistor is ferroelectric only when strain is induced in the gate stack. 
     
     
         11 . The integrated circuit of  claim 7  wherein S 1  is greater than S 2  which is greater than S 3 . 
     
     
         12 . The integrated circuit of  claim 7  wherein the ferroelectric material is selected from the group consisting of BaTiO 3 , Pb[Zr x Ti 1-x ]O 3  (PZT), SrBi 2 Ta 2 O 9  (SBT), SrTiO 3  (STO), Ba 1-x Sr x TiO 3  (BST), PbTiO 3 , EuTiO 3 , CaMnO 3  and BiFeO 3 . 
     
     
         13 . An integrated circuit comprising:
 a first field-effect transistor having a gate stack comprising a first electrically insulating material that is ferroelectric when strain is induced to a first predetermined level, the first field-effect transistor having a first threshold voltage, Vt 1 ;   a second field-effect transistor having a gate stack comprising a second electrically insulating material that is ferroelectric when strain is induced to a second predetermined level, the second field-effect transistor having a second threshold voltage, Vt 2 ; and   a third field-effect transistor having a gate stack, the third field-effect transistor having a third threshold voltage, Vt 3 ,   wherein the first and second electrically insulating materials are the same and the first electrically insulating material is strained to at least the first predetermined level so that the first electrically insulating material is ferroelectric while the second electrically insulating material is unstrained or strained to below the second predetermined level so that the second electrically insulating material is not ferroelectric and wherein the first and second electrically insulating materials are configured to shift Vt 1  relative to Vt 2  and Vt 3  by a predetermined amount such that Vt 1 , Vt 2  and Vt 3  are all set to different predetermined values.   
     
     
         14 . The integrated circuit of  claim 13  wherein the third field-effect transistor comprising a third electrically insulating material that is ferroelectric when strain is induced to a third predetermined level and the third electrically insulating material is different from the first and second electrically insulating materials. 
     
     
         15 . The integrated circuit of  claim 14  wherein the third electrically insulating material is strained at least to the third predetermined level so that it is ferroelectric and the strain induced on the first electrically insulating material is greater than the strain induced on the third electrically insulating material. 
     
     
         16 . The integrated circuit of  claim 15  wherein the strain induced in the gate stacks of the first, second and third field-effect transistors is substantially uniaxial process-induced strain. 
     
     
         17 . The integrated circuit of  claim 13  wherein the gate stack in the third field-effect transistor does not comprise an electrically insulating material that is ferroelectric in the third field-effect transistor or can become ferroelectric in the third field-effect transistor when strain is induced in the gate stack. 
     
     
         18 . The integrated circuit of  claim 13  wherein the first and second electrically insulating materials are ferroelectric only when strain is induced in the gate stack in a predetermined amount, S 1  is greater than S 2  such that the first electrically insulating material is ferroelectric and the second electrically insulating material is not ferroelectric. 
     
     
         19 . The integrated circuit of  claim 18  wherein the gate stack in the third field-effect transistor does not comprise an electrically insulating material that is ferroelectric in the third field-effect transistor or can become ferroelectric in the third field-effect transistor when strain is induced in the gate stack. 
     
     
         20 . The integrated circuit of  claim 13  wherein the first, second and third electrically insulating materials are selected from the group consisting of SrTiO 3  (STO), EuTiO 3 , and CaMnO 3  (CMO).