Semiconductor structure

Abstract

A semiconductor structure comprising a tray, a chip, a first grounding wire and a second grounding wire is provided. The tray has a first surface and a second surface, and there is a height difference existing between the first surface and the second surface. The chip is disposed on the first surface of the tray and has an active surface. The first grounding wire connects the active surface and the second surface. The second grounding wire connects the first surface and the second surface.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a tray having a first surface and a second surface, wherein there is a height difference existing between the first surface and the second surface;   a chip disposed on the first surface of the tray and having an active surface;   a first grounding wire connecting the active surface and the second surface; and   a second grounding wire connecting the first surface and the second surface.   
     
     
         2 . The semiconductor structure according to  claim 1 , further comprising:
 a third grounding wire connecting the active surface and the second surface;   wherein, the first grounding wire, the second grounding wire and the third grounding wire are staggered on the second surface, and the second grounding wire is located between the first grounding wire and the third grounding wire.   
     
     
         3 . The semiconductor structure according to  claim 2 , further comprising:
 a fourth grounding wire connecting the first surface and the second surface;   wherein, the second grounding wire, the third grounding wire and the fourth grounding wire are staggered on the second surface, and the third grounding wire is located between the second grounding wire and the fourth grounding wire.   
     
     
         4 . The semiconductor structure according to  claim 1 , the second surface is located at a height position between the active surface and the first surface. 
     
     
         5 . The semiconductor structure according to  claim 1 , wherein the second surface is higher than the first surface and extended outward relative to the first surface. 
     
     
         6 . The semiconductor structure according to  claim 1 , wherein the tray comprises a chip carrying portion and a bending plate, and the chip carrying portion and the bending plate form a recess. 
     
     
         7 . The semiconductor structure according to  claim 6 , wherein the bending plate of the tray is an intact sidewall. 
     
     
         8 . The semiconductor structure according to  claim 1 , wherein the tray comprises a chip carrying portion, a separation recess and two bending plates, the separation recess separates the two bending plates, and each bending plate comprises:
 a wire carrying portion; and   a connection portion connecting the chip carrying portion and the wire carrying portion.   
     
     
         9 . The semiconductor structure according to  claim 8 , wherein the first surface of the tray has a grounding point, and a first path length, which starts from the grounding point, passes through the chip carrying portion, the connection portion, the wire carrying portion, the first grounding wire and reaches the chip, is larger than a second path length, which starts from the grounding point, passes through the chip carrying portion, the second grounding wire, the wire carrying portion, the first grounding wire and reaches the chip. 
     
     
         10 . The semiconductor structure according to  claim 1 , wherein a first A end and a first B end of the first grounding wire are connected to the active surface and the second surface respectively, a second A end and a second B end of the second grounding wire are connected to the first surface and the second surface respectively, and the second A end of the second grounding wire is located between the first A end and the first B end of the first grounding wire. 
     
     
         11 . The semiconductor structure according to  claim 1 , further comprising:
 a package body encapsulating the tray, the chip, the first grounding wire and the second grounding wire.   
     
     
         12 . The semiconductor structure according to  claim 11 , further comprising:
 an outer lead separated from the tray and extended to an exterior of the package body.