Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same

Abstract

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body fully depleted silicon-on-insulator substrate. The method forms a temporary gate structure over the substrate and forms lightly doped source/drain extension areas around the gate structure. Further, the method includes performing an annealing process on the lightly doped source/drain extension areas. Outdiffusion from the lightly doped source/drain extensions is less than 5 nm during the annealing process. The method includes forming a strain region around the gate structure.

What is claimed is: 
     
         1 . A method for fabricating an integrated circuit comprising:
 providing an ultrathin body fully depleted silicon-on-insulator substrate;   forming a temporary gate structure over the substrate;   forming lightly doped source/drain extension areas around the gate structure;   performing an annealing process on the lightly doped source/drain extension areas, wherein outdiffusion from the lightly doped source/drain extensions is less than  5  nm during the annealing process; and   forming a strain region around the gate structure.   
     
     
         2 . The method of  claim 1  wherein outdiffusion from the lightly doped source/drain extensions is less than 4 nm. 
     
     
         3 . The method of  claim 1  wherein outdiffusion from the lightly doped source/drain extensions is less than 3 nm. 
     
     
         4 . The method of  claim 1  wherein forming the strain region around the gate structure comprises forming the strain region around the gate structure after performing the annealing process. 
     
     
         5 . The method of  claim 1  wherein the lightly doped source/drain extension areas are doped with a first dopant and wherein the method further comprises growing a boron-doped silicon layer free of the first dopant on the lightly doped source/drain extension areas. 
     
     
         6 . The method of  claim 1  wherein forming the compressive strain region around the PFET gate structure comprises growing a boron-doped silicon germanium (SiGe) layer. 
     
     
         7 . The method of  claim 1  wherein forming the compressive strain region around the PFET gate structure comprises growing a boron-doped silicon germanium (SiGe) layer, and wherein the method further comprises growing a boron-doped germanium-free silicon layer overlying the boron-doped SiGe layer. 
     
     
         8 . The method of  claim 1  wherein forming the strain region around the gate structure comprises growing a phosphorus-doped silicon carbon (SiC) layer. 
     
     
         9 . The method of  claim 1  wherein forming the strain region around the gate structure comprises growing a phosphorus-doped silicon carbon (SiC) layer, and wherein the method further comprises growing a phosphorus-doped carbon-free silicon layer overlying the phosphorus-doped SiC layer. 
     
     
         10 . A method for fabricating an integrated circuit comprising:
 providing an ultrathin body fully depleted silicon-on-insulator substrate;   forming a PFET temporary gate structure and an NFET temporary gate structure over the substrate;   forming lightly doped active areas around the gate structures;   performing a diffusionless annealing process on the active areas;   after performing the diffusionless annealing process, forming a compressive strain region around the PFET gate structure; and   after performing the diffusionless annealing process, forming a tensile strain region around the NFET gate structure.   
     
     
         11 . The method of  claim 10  wherein performing the diffusionless annealing process on the active areas comprises limiting outdiffusion from the active areas to less than 4 nm. 
     
     
         12 . The method of  claim 10  further comprising:
 growing a boron-doped germanium-free silicon layer overlying the compressive strain region; and 
 growing a phosphorus-doped carbon-free silicon layer overlying the tensile strain region. 
 
     
     
         13 . The method of  claim 10  wherein forming a compressive strain region around the PFET gate structure comprises growing a boron-doped silicon germanium (SiGe) layer; wherein forming a tensile strain region around the NFET gate structure comprises growing a phosphorus-doped silicon carbon (SiC) layer; and wherein the method further comprises:
 growing a boron-doped germanium-free silicon layer overlying the boron-doped SiGe layer; and 
 growing a phosphorus-doped carbon-free silicon layer overlying the phosphorus-doped SiC layer. 
 
     
     
         14 . A method for fabricating an integrated circuit comprising:
 providing an ultrathin body fully depleted silicon-on-insulator substrate;   forming a PFET temporary gate structure and an NFET temporary gate structure on the substrate;   forming a compressive strain region around the PFET temporary gate structure;   forming a tensile strain region around the NFET temporary gate structure;   replacing the PFET temporary gate structure and the NFET temporary gate structure with high K metal gate HKMG structures.   
     
     
         15 . The method of  claim 14  wherein forming the compressive strain region around the PFET temporary gate structure comprises selectively epitaxially growing an in situ boron-doped (ISBD) silicon germanium (SiGe) region on the semiconductor substrate, and wherein forming the tensile strain region around the NFET temporary gate structure comprises selectively epitaxially growing an in situ phosphorus-doped (ISPD) silicon carbon (SiC) region. 
     
     
         16 . The method of  claim 15  further comprising:
 growing a boron-doped germanium-free silicon layer overlying the SiGe region; and 
 growing a phosphorus-doped carbon-free silicon layer overlying the SiC region. 
 
     
     
         17 . The method of  claim 14  wherein providing the semiconductor substrate comprises providing an ultrathin body fully depleted silicon-on-insulator (SOI) substrate having an undoped SOI layer with a thickness of about 5 nanometers (nm). 
     
     
         18 . The method of  claim 14  further comprising:
 forming lightly doped active areas around the gate structures; and 
 performing a diffusionless annealing process on the active areas. 
 
     
     
         19 . The method of  claim 18  wherein performing the diffusionless annealing process comprises annealing the active areas at a temperature of about 1200° C. to about 1300° C. and for a duration of about 1 ms to about 10 ms. 
     
     
         20 . The method of  claim 14  wherein forming the PFET and NFET temporary gate structures on the substrate comprises:
 forming STI regions in the substrate; 
 depositing a gate oxide layer over the substrate, a polysilicon layer over the gate oxide layer, and alternating oxide and nitride layers over the polysilicon layer; 
 etching the gate oxide, polysilicon, and alternating oxide and nitride layers to form the temporary gate structures.