Transceiver System and Operation Method Thereof

Abstract

A transceiver system which can communicate a plurality of linked partners, and the increase in power consumption by the transceiver system can be minimized. The transceiver system includes a transceiver, and a communication controller. The transceiver is capable of performing transmitted and received data communication with terminal devices. The communication controller is capable of controlling the memory transfer of transmitted and received data. The transceiver system can be set to an operation mode selected from among intermittent- and uninterrupted-operation modes. In the intermittent-operation mode, the transceiver and the communication controller work alternately, whereas in the uninterrupted-operation mode, the transceiver and the communication controller works in parallel. The operation mode of the transceiver system is set according to unique identification data of terminal devices. In a working period of the communication controller in the intermittent-operation mode, the operation of the transceiver is stopped by the control signal.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor integrated circuit, comprising:
 a central processing unit;   a direct memory access controller;   a physical-layer transceiver configured to execute transmitted and received data communications with a plurality of terminal devices; and   a logical-layer media access controller operable to control the central processing unit and the direct memory access controller, and configured to control memory transfer of transmitted and received data which is executed by the direct memory access controller and which is controlled according to operation control by the central processing unit,   wherein the semiconductor integrated circuit can be set in one operation mode selected from among an intermittent-operation mode and an uninterrupted-operation mode,   wherein, in the intermittent-operation mode, an operation of the physical-layer transceiver and an operation of the logical-layer media access controller are executed alternately, and   wherein, in the uninterrupted-operation mode, an operation of the physical-layer transceiver and an operation of the logical-layer media access controller are executed in parallel.   
     
     
         22 . The semiconductor integrated circuit according to  claim 21 ,
 wherein the semiconductor integrated circuit is set in the one operation mode according to unique identification data of the plurality of terminal devices.   
     
     
         23 . The semiconductor integrated circuit according to  claim 22 ,
 wherein the unique identification data include packet header data of the data transmitted by the plurality of terminal devices.   
     
     
         24 . The semiconductor integrated circuit according to  claim 23 ,
 wherein the packet header data include address data of the plurality of terminal devices.   
     
     
         25 . The semiconductor integrated circuit according to  claim 24 ,
 wherein the logical-layer media access controller includes an address-setting register for storing the address data as the unique identification data for setting the operation mode of the semiconductor integrated circuit to the uninterrupted-operation mode, which is the one operation mode.   
     
     
         26 . The semiconductor integrated circuit according to  claim 21 ,
 wherein, in the intermittent-operation mode, supply of an operating-source voltage to the physical-layer transceiver is stopped according to a control signal generated by the logical-layer media access controller, thereby to stop the operation of the physical-layer transceiver for a period where the operation of the logical-layer media access controller is executed.   
     
     
         27 . The semiconductor integrated circuit according to  claim 21 ,
 wherein the logical-layer media access controller includes a buffer memory operable to buffer transmitted data sent from the plurality of terminal devices,   wherein the transmitted data is buffered in the buffer memory during the operation of the physical-layer transceiver in the intermittent-operation mode, and   wherein the transmitted data buffered in the buffer memory are read out during the operation of the logical-layer media access controller in the intermittent-operation mode.   
     
     
         28 . The semiconductor integrated circuit according to  claim 27 ,
 wherein, during the operation of the logical-layer media access controller in the intermittent-operation mode, the transmitted data read from the buffer memory are subjected to the memory transfer by the direct memory access controller.   
     
     
         29 . The semiconductor integrated circuit according to  claim 21 ,
 wherein the logical-layer media access controller can be supplied with an external control signal provided from outside the transceiver system, and   wherein the logical-layer media access controller is capable of forcibly setting an operation mode of the transceiver system to the uninterrupted-operation mode in response to the external control signal.   
     
     
         30 . A semiconductor integrated circuit for use with a plurality of terminal devices, the semiconductor integrated circuit, comprising:
 a central processing unit;   a direct memory access controller;   a physical-layer transceiver configured to transmit data to, and receive data from, a plurality of terminal devices; and   a logical-layer media access controller operable to control the central processing unit and the direct memory access controller, and configured to control memory transfer of transmitted and received data which is executed by the direct memory access controller,   wherein the semiconductor integrated circuit can be set in one operation mode selected from among an intermittent-operation mode and an uninterrupted-operation mode,   wherein, in the intermittent-operation mode, an operation of the physical-layer transceiver and an operation of the logical-layer media access controller are executed alternately,   wherein, in the uninterrupted-operation mode, an operation of the physical-layer transceiver and an operation of the logical-layer media access controller are executed in parallel,   wherein the logical-layer media access controller includes an address-setting register for storing address data of the plurality of terminal devices for setting the operation mode of the semiconductor integrated circuit to the uninterrupted-operation mode, which is the one operation mode.   
     
     
         31 . The semiconductor integrated circuit according to  claim 30 ,
 wherein the logical-layer media access controller checks the address data set in the address-setting register and packet header data of data transmitted by one of the plurality of terminal devices to set the operation mode of the semiconductor integrated circuit to the uninterrupted-operation mode, which is the one operation mode, when the address data set in the address-setting register is coincident with address data in the packet header data.