Implementing buried fet below and beside finfet on bulk substrate

Abstract

A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor.

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         16 . A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:
 a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing an enhanced transistor topology enabling enhanced current capability comprising:   a fin field effect transistor (FinFET); said FinFET formed on a semiconductor substrate; said FinFET having in-line source and drain regions formed without a dog-bone shape and a gate region formed on a gate dielectric with first and second gate extensions extending past opposing sides of said in-line source and drain regions;   a first field effect transistor (FET) formed in said semiconductor substrate beside and under said FinFET and a second FET formed in said semiconductor substrate beside and under said FinFET; each of said first FET and said second FET having buried source and drain diffusions formed in said semiconductor substrate on the opposing sides of said in-line source and drain regions with angled implants used to dope said buried source and drain diffusions and FinFET; and said first and second gate extensions of said FinFET providing a gate of said first FET and said second FET, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.   
     
     
         17 . The design structure of  claim 16 , wherein the design structure comprises a netlist, which describes said circuit. 
     
     
         18 . The design structure of  claim 16 , wherein the design structure resides on the non-transitory machine readable medium as a data format used for the exchange of layout data of integrated circuits. 
     
     
         19 . The design structure of  claim 16 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. 
     
     
         20 . The design structure of  claim 16 , wherein said FinFET, said first FET and said second FET are connected in parallel, having a common source connection and a common drain connection. 
     
     
         21 . The design structure of  claim 20 , wherein each of said common source connection and said common drain connection include a bar contact. 
     
     
         22 . The design structure of  claim 16 , wherein said semiconductor substrate includes a bulk substrate.