Method of fabricating isolating semiconductor structures

Abstract

Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor structure comprising:
 forming a plurality of first trenches in a semiconductor substrate,   forming at least a second trench in the semiconductor substrate,   applying a migration process such that the first trenches are changed to a continuous semiconductor layer extending substantially in parallel to a main surface of the semiconductor substrate and being separated from the underlying part of the substrate in a direction perpendicular to the main surface by a continuous cavity, wherein the continuous cavity is connected to at least a first opening in the substrate surface formed by the at least second trench,   forming a first dielectric layer to fill at least an upper portion of the at least first opening while leaving the cavity substantially unfilled,   removing portions of the continuous semiconductor layer to form at least a second opening connecting the substrate surface to the cavity,   and filling at least an upper portion of the at least second opening with a second dielectric layer such that the cavity is sealed.   
     
     
         2 . The method according to  claim 1 , wherein the migration process comprises a heat treatment in a hydrogen atmosphere. 
     
     
         3 . The method according to  claim 1 , wherein the continuous semiconductor material layer is a crystalline semiconductor layer formed by a recrystallization of the migrated material of the first part of the semiconductor structure. 
     
     
         4 . The method according to  claim 1 , wherein the first and the second trenches are formed concurrently. 
     
     
         5 . The method according to  claim 1 , wherein the minimum width of the second trench is larger than a minimum width of a first trench. 
     
     
         6 . The method according to  claim 1 , wherein the first and second trenches are connected to each other. 
     
     
         7 . The method according to  claim 1 , wherein the first trenches are layed out as stripes. 
     
     
         8 . The method according to  claim 1  wherein the first trenches have a circular layout. 
     
     
         9 . The method according to  claim 1 , wherein the pressure inside the sealed cavity is defined by the pressure conditions during the second dielectric layer deposition. 
     
     
         10 . The method according to  claim 1  wherein the second opening is defined by a masking step. 
     
     
         11 . The method according to  claim 1 , wherein the first dielectric layer is also formed on the surface of the continuous semiconductor layer located opposite to the cavity. 
     
     
         12 . The method according to  claim 11 , wherein, prior to removing portions of the continuous semiconductor layer to form the second opening, the additional step of removing a portion of the first dielectric layer formed on the surface of the semiconductor layer is performed. 
     
     
         13 . The method according to  claim 1  wherein the additional step of planarizing the first dielectric layer is performed. 
     
     
         14 . The method according to  claim 1 , wherein at least one of the first and second dielectric layer formations contains a non-conformal deposition step. 
     
     
         15 . The method according to  claim 14 , wherein the cavity remains substantially unfilled after the first and second dielectric layer formation. 
     
     
         16 . The method according to  claim 14 , wherein only the upper part of the first opening is filled by the first dielectric layer such that the cavity extends below the first opening after the fill. 
     
     
         17 . The method according to  claim 14 , wherein only the upper part of the second opening is filled by the second dielectric layer such that the cavity extends below the second opening after the fill. 
     
     
         18 . The method according to  claim 14 , wherein at least part of the first dielectric layer is formed by a HDP deposition process. 
     
     
         19 . The method according to  claim 14 , wherein at least part of the second dielectric layer is formed by an HDP deposition process. 
     
     
         20 . The method according to  claim 14  wherein the nonconformal deposition process comprises an HDP deposition process comprising a step configured for increased redeposition rate at the sidewalls of an opening below the substrate surface. 
     
     
         21 . The method according to  claim 14 , wherein at least one of the first and second dielectric layers contains BPSG. 
     
     
         22 . The method according to  claim 1 , wherein at least a part of the continuous semiconductor layer forms a flexible element of a MEMS device. 
     
     
         23 . The method according to  claim 1 , wherein at least a part of the continuous semiconductor layer is part of a pressure sensor. 
     
     
         24 . The method according to  claim 1 , wherein at least a part of the continuous semiconductor layer is used as part of a bolometer. 
     
     
         25 . The method according to  claim 1  wherein the at least first opening and the at least second opening define a region which completely surrounds a part of the continuous semiconductor region. 
     
     
         26 . A method of fabricating a semiconductor structure comprising:
 forming a plurality of first trenches in a semiconductor substrate,   applying a migration process such that the first trenches are changed to a continuous semiconductor layer extending substantially in parallel to a main surface of the semiconductor substrate and being separated from the underlying part of the substrate in a direction perpendicular to the main surface by a continuous cavity,   forming at least a first opening in the substrate surface which connects the substrate surface to the continuous cavity in the semiconductor substrate,   forming a first dielectric layer to fill at least an upper portion of the at least first opening while leaving the cavity essentially unfilled,   removing portions of the semiconductor material to form at least a second opening connecting the substrate surface to the cavity,   and filling at least an upper portion of the at least second opening with a second dielectric layer such that the cavity is sealed.