High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same

Abstract

An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a coreless mounting substrate   an interposer disposed on the coreless mounting substrate, wherein the interposer includes:
 a die side and a land side that is parallel planar to the die side; 
 a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate; 
 an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; and 
 a trace in the coreless mounting substrate. 
   
     
     
         2 . The apparatus of  claim 1 , further including a chip disposed on the coreless mounting substrate within the recess footprint and coupled to the trace. 
     
     
         3 . The apparatus of  claim 1 , wherein the coreless mounting substrate exhibits a first stiffness and the interposer exhibits a second stiffness that is greater than the first stiffness. 
     
     
         4 . The apparatus of  claim 1 , wherein the recess footprint is centered on a symmetry line that equally bisects the coreless substrate. 
     
     
         5 . (canceled) 
     
     
         6 . The apparatus of  claim 1 , wherein the recess is a first recess, the apparatus further including a second recess spaced apart from the first recess, and wherein the second recess communicates to the die side and the land side. 
     
     
         7 . The apparatus of  claim 1 , wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and   a processor chip disposed on the coreless substrate in the first recess.   
     
     
         8 . (canceled) 
     
     
         9 . The apparatus of  claim 1 , further including:
 a first die disposed on the coreless substrate within the recess footprint; and a subsequent die also disposed on the coreless substrate within the recess footprint.   
     
     
         10 . The apparatus of  claim 1 , wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and   a subsequent interposer disposed above the first interposer.   
     
     
         11 . The apparatus of  claim 1 , wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;   a subsequent interposer disposed above the first interposer;   a first die disposed on the coreless substrate in the first recess; and   a second die disposed on the coreless substrate in the second recess, and where the first die and the second die are different respective sizes.   
     
     
         12 . (canceled) 
     
     
         13 . The apparatus of  claim 1 , wherein the coreless substrate is a thin core substrate. 
     
     
         14 . An apparatus, comprising:
 a coreless mounting substrate;   an interposer disposed on the coreless mounting substrate, wherein the interposer includes:
 a die side and a land side that is parallel planar to the die side; 
 a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate; 
 an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; 
 a chip disposed on the coreless substrate within the footprint; 
   an inter-package solder bump in contact with the interconnect channel; and   a top chip package including a top package substrate and a top die disposed on the top package substrate, wherein the top package substrate is in contact with the inter-package solder bump.   
     
     
         15 . The apparatus of  claim 14 , wherein the recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate. 
     
     
         16 . The apparatus of  claim 14 , wherein the recess is a first recess, the apparatus further including a second recess spaced apart from the first recess, and wherein the second recess communicates to the die side and the land side. 
     
     
         17 . The apparatus of  claim 14 , wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and   wherein the chip is a processor chip disposed on the coreless substrate in the first recess.   
     
     
         18 . The apparatus of  claim 14 , wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and   wherein the first recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate.   
     
     
         19 . The apparatus of  claim 14 , further including:
 wherein the chip is a first die disposed on the coreless substrate within the recess footprint; and   a subsequent die also disposed on the coreless substrate within the recess footprint.   
     
     
         20 . The apparatus of  claim 14 , wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and   a subsequent interposer disposed above the first interposer.   
     
     
         21 . The apparatus of  claim 14 , wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;   a subsequent interposer disposed above the first interposer;   wherein the chip is a first die disposed on the coreless substrate in the first recess; and a second die disposed on the coreless substrate in the second recess, and where the first die and the second die are different respective sizes.   
     
     
         22 . The apparatus of  claim 14 , wherein the recess is a first recess, the apparatus further including:
 a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;   wherein the die is a first chip disposed on the coreless substrate in the first recess; and a second chip disposed on the coreless substrate in the second recess, wherein the second chip is wire-bonded to the coreless substrate.   
     
     
         23 . A computing system, comprising:
 a coreless mounting substrate;   an interposer disposed on the coreless mounting substrate, wherein the interposer includes:
 a die side and a land side that is parallel planar to the die side; 
 a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate; 
 an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; 
 a chip disposed on the coreless substrate within the footprint; 
   an inter-package solder bump in contact with the interconnect channel; and   a top chip package including a top package substrate and a top die disposed on the top package substrate, wherein the top package substrate is in contact with the inter-package solder bump; and   external memory coupled to the die.   
     
     
         24 . The computing system of  claim 23 , wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio. 
     
     
         25 . A process comprising:
 forming an interconnect channel in an interposer;   plating the interconnect channel with an electrical conductor;   removing metal spaced apart from the interconnect channel;   filling the interconnect channel with an electrical conductor;   forming a recess in the interposer to accommodate a microelectronic die;   mating the interposer to a coreless mounting substrate, wherein the recess projects a footprint onto the coreless substrate; and   attaching a microelectronic die to the coreless mounting substrate at the recess footprint.   
     
     
         26 . The process of  claim 25 , further including forming an underfill between the microelectronic die and the coreless substrate. 
     
     
         27 . The process of  claim 25 , wherein attaching the microelectronic die precedes mating the interposer to the coreless mounting substrate, and further including forming an underfill between the microelectronic die and the coreless substrate. 
     
     
         28 . The process of  claim 25 , wherein the interposer is part of an unsingulated array of interposers, the method further including singulating the array of interposers after mating the interposer to the coreless mounting substrate. 
     
     
         29 . The process of  claim 25 , wherein the interposer is part of an unsingulated array of interposers, the method further including singulating the array of interposers after attaching the microelectronic die to the coreless mounting substrate at the recess. 
     
     
         30 . The process of  claim 25 , wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:
 forming an inter-package solder bump at the electrical conductor; and assembling a top package to the bottom package by coupling the top package to the inter-package solder bump.   
     
     
         31 . The process of  claim 25 , wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:
 forming an inter-package solder bump at the electrical conductor; and assembling a top package to the bottom package by coupling the top package to the inter-package solder bump, wherein the top package includes a top mounting substrate and a wire-bonded die disposed on the top mounting substrate.   
     
     
         32 . The process of  claim 25 , wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:
 forming an inter-package solder bump at the electrical conductor; and   assembling a top package to the bottom package by coupling the top package to the inter-package solder bump, wherein the top package includes a top mounting substrate and a flip-chip die disposed on the top mounting substrate.   
     
     
         33 . The process of  claim 25 , wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:
 forming an inter-package solder bump at the electrical conductor; and   assembling a top package to the bottom package by coupling the top package to the inter-package solder bump, wherein the top package includes a top mounting substrate, a flip-chip die disposed above the top mounting substrate, and a wire-bonded die disposed above the top mounting substrate.   
     
     
         34 . An apparatus, comprising:
 in a bottom package a first die flip-chip mounted upon a first mounting substrate at a chip-bonding pad on a die side thereof, wherein the first mounting substrate is bumped with a land side bump on a land side thereof;   in a top package a top first die wirebonded to a top mounting substrate, and a wirebonded top subsequent die also mounted on the top mounting substrate;   wherein the top package is electrically coupled to the bottom package;   an overmold material that contacts the top mounting substrate, the top first die, and the top subsequent die;   wherein the first die is disposed between the first mounting substrate and the top mounting substrate.   
     
     
         35 . The apparatus of  claim 34 , wherein the top package and the bottom package are electrically coupled through an interposer. 
     
     
         36 . The apparatus of  claim 34 , wherein the top package includes a core. 
     
     
         37 . The apparatus of  claim 34 , wherein the top package includes a core and wherein the bottom package is coreless. 
     
     
         38 . The apparatus of  claim 34 , wherein the top package subsequent die is disposed laterally symmetrical and also vertical to the top package first die. 
     
     
         39 . An apparatus, comprising:
 in a bottom package a first die flip-chip mounted upon a first mounting substrate at a chip-bonding pad on a die side thereof, wherein the first mounting substrate is bumped with a land side bump on a land side thereof;   in top POP package a top package first die disposed on a top mounting substrate, and a top package subsequent die disposed above the top package first die;   wherein the top package is electrically coupled to the bottom package through a POP connector;   an overmold material that contacts the first mounting substrate, the top mounting substrate, the top package first die, the top package subsequent die;   wherein the first die is disposed between the first mounting substrate and the top mounting substrate.   
     
     
         40 . The apparatus of  claim 39 , wherein the top package and the bottom package are electrically coupled through an interposer. 
     
     
         41 . The apparatus of  claim 39 , wherein the top package includes a core. 
     
     
         42 . The apparatus of  claim 39 , wherein the top package includes a core and wherein the bottom package is coreless. 
     
     
         43 . The apparatus of  claim 39 , wherein the top package subsequent die is disposed laterally symmetrical and also vertical to the top package first die.