Self-bias emitter circuit

Abstract

Self-bias emitter circuit configurations can use the amplitude of an input AC carrier signal to provide a DC bias voltage across an emitter for suitable operation. A self-bias emitter circuit can include a transductor with primary matched with an amplifier, while secondary can be matched to the emitter. Self-bias emitter circuit can also include a full-wave bridge rectifier or a center tap inductor in conjunction with two diodes to rectify the AC carrier signal into a corresponding DC voltage. This DC voltage can be subsequently filtered by a capacitor to provide a steady DC bias voltage across the emitter. Sufficiently small, decoupling capacitors can be installed at each side of the full-wave rectifier in order to decouple the DC bias voltage, while a sufficiently large capacitor can be installed between the emitter and secondary for preventing the applied DC bias voltage from flowing back to secondary.

What is claimed is: 
     
         1 . An emitter circuit for providing a bias voltage, comprising:
 an emitter;   a full-wave bridge rectifier configured to convert an alternating current (AC) carrier signal into a corresponding direct current (DC) voltage; and   a filter capacitor configured to reduce variations of the DC voltage at an output of the full-wave bridge rectifier in order to provide a DC bias voltage across the emitter.   
     
     
         2 . The emitter circuit of  claim 1 , wherein the circuit is configured to receive the AC carrier signal as input and rectify the AC carrier signal into a steady DC bias voltage. 
     
     
         3 . The emitter circuit of  claim 1 , wherein the DC bias voltage is applied across the emitter without affecting carrier information used by the emitter to emit parametric information. 
     
     
         4 . The emitter circuit of  claim 1 , further comprising a transductor with a primary winding and a secondary winding, the transductor configured to match an impedance of the primary winding to an impedance of an amplifier with the secondary winding configured to form a part of a parallel resonant circuit with the emitter. 
     
     
         5 . The emitter circuit of  claim 4 , further comprising a decoupling capacitor configured to decouple the DC bias voltage from the secondary winding and to avoid shunting the AC carrier signal into the full-wave bridge rectifier. 
     
     
         6 . The emitter circuit of  claim 4 , further comprising a capacitor configured to prevent the DC bias voltage from flowing back to the secondary winding. 
     
     
         7 . The emitter circuit of  claim 2 , wherein the AC carrier signal includes a modulated AC carrier signal or an unmodulated AC carrier signal. 
     
     
         8 . The emitter circuit of  claim 1 , wherein the emitter circuit forms a part of a parametric speaker. 
     
     
         9 . The emitter circuit of  claim 1 , wherein the DC bias voltage can correspond with a peak of the AC carrier signal. 
     
     
         10 . An emitter circuit for providing a bias voltage, comprising;
 an emitter;   a transductor including a primary winding and a secondary winding, the secondary winding including a first portion and a second portion;   a full-wave bridge rectifier coupled to the second portion of the secondary winding, the full-wave bridge rectifier operable to convert an alternating current (AC) carrier signal into a corresponding direct current (DC) voltage; and   a filter capacitor configured to smooth the corresponding DC voltage in order to provide a DC bias voltage across the emitter.   
     
     
         11 . The emitter circuit of  claim 10 , wherein a number of turns of the first portion of the secondary winding and the second portion of the second secondary winding is determined based on a desired amplitude of the DC bias voltage. 
     
     
         12 . The emitter circuit of  claim 10 , wherein the transductor is configured to:
 match the primary winding to the amplifier;   couple the first portion of the secondary winding to the full-wave bridge rectifier to provide step-up voltage conversion, wherein the first portion of the secondary winding has a higher number of turns relative to the second portion of the secondary winding; and   match the second portion of the secondary winding to the emitter.   
     
     
         13 . The emitter circuit of  claim 12 , wherein the step-up voltage conversion provides the DC bias voltage across the emitter. 
     
     
         14 . The emitter circuit of  claim 10 , wherein the emitter circuit includes a center tapped inductor to provide full-wave rectification of the AC carrier signal. 
     
     
         15 . The emitter circuit of  claim 10 , wherein the emitter circuit includes a voltage doubler used in conjunction with the filter capacitor for providing the DC bias voltage to the emitter. 
     
     
         16 . The emitter circuit of  claim 10 , further comprising a diode to limit an amplitude of the DC bias voltage applied across the emitter. 
     
     
         17 . A method for providing a bias voltage across an emitter, the method comprising:
 receiving an alternating current (AC) carrier signal at an emitter circuit, the emitter circuit including a transductor with a primary winding and a secondary winding;   converting the AC carrier signal into a corresponding direct current (DC) voltage; and   reducing variations of the DC voltage to provide a DC bias voltage across the emitter included in the emitter circuit.   
     
     
         18 . The method of  claim 17 , further comprising:
 matching the primary winding of the transductor with an impedance of an amplifier; and   matching the secondary winding of the transductor with an impedance of the emitter to provide a chosen resonant point. Same change here   
     
     
         19 . The method of  claim 18 , further comprising decoupling the DC bias voltage from the secondary winding to avoid shunting the AC carrier signal into a full-wave bridge rectifier associated with the emitter circuit. 
     
     
         20 . The method of  claim 18 , further comprising preventing the DC bias voltage from flowing back to the secondary winding of the transductor.