Two terminal resistive switching device structure and method of fabricating

Abstract

A semiconductor device having a memory device includes a semiconductor substrate, a first dielectric layer disposed above the semiconductor substrate, a first adhesion layer disposed upon the first dielectric layer, a bottom wiring metal disposed upon the first adhesion layer, a first barrier layer disposed upon the bottom wiring metal, a resistive switching material disposed in electrical contact with the first barrier layer, wherein the resistive switching material comprises a silicon material having a plurality of defect regions, a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles, a second barrier layer disposed upon the conductive metal material, a top wiring metal disposed upon the second barrier layer, and wherein at least some of the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material.

What is claimed is: 
     
         1 . A semiconductor device including a memory device comprising:
 a semiconductor substrate;   a first dielectric layer disposed above the semiconductor substrate;   a first adhesion layer disposed upon the first dielectric layer;   a bottom wiring metal disposed upon the first adhesion layer;   a first barrier layer disposed upon the bottom wiring metal;   a resistive switching material disposed in electrical contact with the first barrier layer, wherein the resistive switching material comprises a silicon material having a plurality of defect regions;   a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles;   a second barrier layer disposed upon the conductive metal material;   a top wiring metal disposed upon the second barrier layer; and   wherein at least some of the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material.   
     
     
         2 . The semiconductor device of  claim 1  wherein the first barrier layer is selected from a group consisting of: titanium, titanium nitride, tantalum, tantalum nitride, tungsten and tungsten nitride. 
     
     
         3 . The semiconductor device of  claim 1  wherein the bottom wiring metal comprises copper. 
     
     
         4 . The semiconductor device of  claim 1  wherein the resistive switching material comprises un-doped amorphous silicon. 
     
     
         5 . The semiconductor device of  claim 1  wherein the conductive metal material is CMOS fabrication compatible. 
     
     
         6 . The semiconductor device of  claim 1   wherein the conductive metal material comprises aluminum; and   wherein a plurality of aluminum particles are disposed within defect regions of the resistive switching material and form a filament structure.   
     
     
         7 . The semiconductor device of  claim 6  wherein a resistance of the resistive switching material is associated with a filament length of the filament structure. 
     
     
         8 . The semiconductor device of  claim 1  further comprising a contact material layer disposed between and in contact with the first barrier layer and with the resistive switching material. 
     
     
         9 . The semiconductor device of  claim 8  wherein the contact material is selected from a group consisting of: a doped polysilicon and a doped semiconductor material. 
     
     
         10 . The semiconductor device of  claim 1   wherein the semiconductor substrate comprises a plurality of CMOS devices formed therein;   wherein the memory device comprises the resistive switching material and the conductive metal material; and   wherein the memory device is coupled to at least a CMOS device from the plurality of CMOS devices.   
     
     
         11 . A semiconductor device including a memory device comprising:
 a semiconductor substrate comprising a plurality of CMOS devices formed therein;   a first dielectric layer disposed above the semiconductor substrate;   a bottom wiring structure formed upon the first dielectric layer, comprising:   a first adhesion layer disposed upon the first dielectric layer;   a bottom wiring metal disposed upon the first adhesion layer; and   a second adhesion layer disposed upon the bottom wiring metal;   the memory device disposed upon the bottom wiring structure, comprising:   a resistive switching material disposed in electrical contact with the bottom wiring structure, wherein the resistive switching material comprises a silicon material having a plurality of defect regions;   a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles; and   wherein at least a group of conductive metal particles from the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material, wherein the group of conductive metal particles comprises a filament structure; and   a top wiring structure formed upon the memory device, comprising:   a third adhesion layer disposed upon the memory device; and   a top wiring metal disposed upon the second barrier layer;   wherein the memory device is coupled to at least a CMOS device from the plurality of CMOS devices.   
     
     
         12 . The semiconductor device of  claim 11  wherein the first barrier layer is selected from a group consisting of: titanium, titanium nitride, tantalum, tantalum nitride, tungsten and tungsten nitride. 
     
     
         13 . The semiconductor device of  claim 12  wherein the bottom wiring metal comprises copper. 
     
     
         14 . The semiconductor device of  claim 11  wherein the resistive switching material comprises un-doped amorphous silicon. 
     
     
         15 . The semiconductor device of  claim 11  wherein the conductive metal material is CMOS fabrication compatible. 
     
     
         16 . The semiconductor device of  claim 15  wherein the conductive metal material comprises aluminum. 
     
     
         17 . The semiconductor device of  claim 11  wherein a resistance of the memory device is associated with a filament length of the filament structure. 
     
     
         18 . The semiconductor device of  claim 11  wherein the memory device further comprises a contact material layer disposed between and in contact with the bottom wiring structure and with the resistive switching material. 
     
     
         19 . The semiconductor device of  claim 18  wherein the contact material is selected from a group consisting of: a doped polysilicon and a doped semiconductor material. 
     
     
         20 . The semiconductor device of  claim 11   wherein the bottom wiring metal and the top wiring metal each comprise copper;   wherein the first adhesion layer and the second adhesion layer are each selected from a group consisting of: tungsten nitride, titanium, titanium nitride, tantalum and tantalum nitride; and   wherein the conductive metal material comprises aluminum.