Nonvolatile memory device using semiconductor nanocrystals and method of forming same

Abstract

A method of forming a field effect transistor includes forming a source region and a drain region in a semiconductor material, forming a channel region between the source region and the drain region, forming an insulating layer over the channel region, forming a floating gate layer of electrically conducting material over the insulating layer, forming a layer of an insulating material over the floating gate layer, and forming a gate electrode overlying the layer of insulating material.

What is claimed is: 
     
         1 . A method of forming a field effect transistor, said method comprising:
 forming a source region and a drain region in a semiconductor material;   forming a channel region between said source region and said drain region;   forming an insulating layer over said channel region;   forming a floating gate layer of an electrically conducting material over said insulating layer;   forming a layer of an insulating material over said floating gate layer; and   forming a gate electrode overlying said layer of insulating material.   
     
     
         2 . The method of  claim 1 , wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is one of templated and defined by a self-assembled material. 
     
     
         3 . The method of  claim 2 , wherein said nanoparticles comprise a substantially uniform diameter, said nanoparticles including diameters in a range from 2 nanometers to 30 nanometers, with size distributions no greater than 15% of a mean diameter of the nanoparticles. 
     
     
         4 . The method of  claim 3 , wherein said nanoparticles comprise a substantially uniform center-to-center spacing between said nanoparticles. 
     
     
         5 . The method of  claim 4 , wherein said nanoparticle density is greater than 10 10 /cm 2 . 
     
     
         6 . The method of  claim 1 , wherein said floating gate layer comprises a plurality of discrete nanoparticles having a substantially uniform diameter, said nanoparticles including diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of a mean diameter of the nanoparticles. 
     
     
         7 . The method of  claim 1 , wherein said floating gate layer comprises a plurality of discrete nanoparticles having a substantially uniform center-to-center spacing between said nanoparticles. 
     
     
         8 . The method of  claim 1 , wherein said floating gate layer comprises a plurality of discrete nanoparticles, and
 wherein said nanoparticle density is greater than 10 10 /cm 2 .   
     
     
         9 . A method of making a uniform nanoparticle array, said method comprising:
 performing a diblock copolymer thin film self assembly over a dielectric on silicon;   creating a porous polymer film; and   transferring a pattern into said dielectric.   
     
     
         10 . The method of  claim 9 , further comprising:
 selectively growing epitaxial silicon off a silicon substrate.   
     
     
         11 . The method of  claim 9 , further comprising:
 selectively growing epitaxial silicon off a silicon substrate from within pores.   
     
     
         12 . The method of  claim 9 , further comprising:
 selectively growing epitaxial silicon off a silicon substrate from within pores to create a silicon nanoparticle array.   
     
     
         13 . A method of making a nanoparticle array, comprising:
 replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film; and   anisotropically and selectively etching a material on said porous dielectric film.   
     
     
         14 . The method of  claim 13 , wherein said nanoparticle array comprises a uniform nanoparticle array, and
 wherein said self-assembled film comprises a polymer template.   
     
     
         15 . The method of  claim 13 , wherein said replicating is performed without deteriorating a dimension and uniformity inherent in the self-assembled film. 
     
     
         16 . The method of  claim 13 , further comprising:
 shrinking nanoparticles in said nanoparticle array by oxidation or etching.   
     
     
         17 . The method of  claim 13 , further comprising:
 one of shrinking pores with a spacer process prior to forming said nanoparticles, and enlarging pores by etching prior to said forming said nanoparticles.   
     
     
         18 . The method of  claim 13 , further comprising:
 shrinking nanoparticles in the nanoparticle array.   
     
     
         19 . The method of  claim 13 , further comprising:
 shrinking nanoparticles in the nanoparticle array by oxidation.   
     
     
         20 . The method of  claim 13 , further comprising:
 shrinking nanoparticles in the nanoparticle array by etching.