Encoder, decoder, and transmission system

Abstract

An encoder including an encoder configured to perform encoding using a clock embedded encoding method, and a comparator configured to compare unencoded first and second input data, and in response to the unencoded first and second input data being identical, to output first encoded data into which the first input data is encoded by the encoder and to output, successively to the first encoded data, a special code as second encoded data into which the second input data is encoded. The special code is not stipulated in the clock embedded encoding method and exhibits a higher bit change rate than that produced according to the clock embedded encoding method.

What is claimed is: 
     
         1 . An encoder comprising:
 an encoder configured to perform encoding using a clock embedded encoding method; and   a comparator configured to compare unencoded first and second input data, and in response to the unencoded first and second input data being identical, to output first encoded data into which the first input data is encoded by the encoder and to output, successively to the first encoded data, a special code as second encoded data into which the second input data is encoded,   wherein the special code is not stipulated in the clock embedded encoding method and exhibits a higher bit change rate than that produced according to the clock embedded encoding method.   
     
     
         2 . The encoder according to  claim 1 , wherein:
 the first and second input data include display data according to which an image is displayed on a display device,   the comparator is further configured to output, according to the display data, a blanking signal indicating a blanking period, during the blanking period other than a display period during which the image is displayed on the display device according to the display data, and   during the display period, a signal identical to the blanking signal or a signal whose logic levels are reverses of those of the blanking signal is output.   
     
     
         3 . The encoder according to  claim 1 , wherein in response to the first and second input data being different from each other, the comparator outputs data, into which the second input data is encoded by the encoder, as the second encoded data. 
     
     
         4 . The encoder according to  claim 1 , further comprising:
 a memory configured to retain the first input data out of the sequentially inputted first and second input data;   wherein the second input data is compared with the first input data retained by the memory, and   the comparator outputs the first and second encoded data on the basis of the comparison of the second input data and the first input data retained in the memory.   
     
     
         5 . The encoder according to  claim 1 , wherein:
 in response to third input data that has not been encoded by the encoder being identical to the first input data, the comparator outputs a second special code, which is different from the special code, as third encoded data, into which the third input data is encoded, successively to the second encoded data.   
     
     
         6 . The encoder according to  claim 5 , wherein in response to the first and third input data being different from each other, the comparator outputs data, into which the third input data is encoded by the encoder, as the third encoded data. 
     
     
         7 . The encoder according to  claim 5 , further comprising:
 a memory that retains the first input data out of the sequentially inputted first, second, and third data,   wherein the third input data is compared with the first input data retained by the memory, and   the comparator outputs the first and third encoded data on the basis of the comparison of the third input data and the first input data retained in the memory.   
     
     
         8 . The encoder according to  claim 1 , wherein in response to the successive first and second encoded data exhibiting a low bit change rate, the comparator outputs the special code. 
     
     
         9 . The encoder according to  claim 1 , wherein the clock embedded encoding method is an mBnB encoding method for encoding data of m bits long into n bits where n is larger than m. 
     
     
         10 . A decoder comprising:
 a decoder configured to decode according to a clock embedded encoding method;   a memory configured to retain decoded data produced by the decoder; and   a state decision circuit configured to, in response to successive undecoded first and second encoded data where the second encoded data is a special code, output first decoded data into which the first encoded data is decoded by the decoder and output data identical to the first decoded data and retained by the memory, as second decoded data into which the second encoded data is decoded,   wherein the special code is not stipulated in the clock embedded encoding method and exhibits a higher bit change rate than that produced according to the predetermined encoding method does.   
     
     
         11 . The decoder according to  claim 10 , wherein in response to the second encoded data being different from the special code, the state decision circuit outputs, as the second decoded data, data into which the second encoded data is decoded by the decoder. 
     
     
         12 . The decoder according to  claim 10 , wherein:
 the first and second decoded data are display data according to which an image is displayed on a display device; and   during a display period during which the image is displayed on the display device according to the display data, the state decision circuit outputs the first and second decoded data that are associated with the first and second encoded data respectively.   
     
     
         13 . The decoder according to  claim 12 , wherein in response to a data start signal that indicates a beginning of the display period being input, the state decision circuit regards a certain period, which begins with the data start signal, as the display period, and outputs the first and second decoded data that are associated with the first and second encoded data respectively. 
     
     
         14 . The decoder according to  claim 10 , wherein in response to third encoded data that succeeds the first and second encoded data being a second special code different from the special code, the state decision circuit outputs, as third decoded data into which the third encoded data is decoded, data identical to the first decoded data and retained by the memory. 
     
     
         15 . The decoder according to  claim 14 , wherein in response to the third encoded data being different from the special code, the state decision circuit outputs, as the third decoded data, data into which the third encoded data is decoded by the decoder. 
     
     
         16 . The decoder according to  claim 10 , wherein the clock embedded encoding method is an mBnB encoding method for encoding data of m bits long into n bits where n is larger than m. 
     
     
         17 . A transmission system having an encoder and a decoder coupled to each other over a transmission line, wherein:
 the encoder comprises:
 an encoder configured to perform encoding using a clock embedded encoding method; and 
 a comparator configured to compare unencoded first and second input data, and in response to the unencoded first and second input data being identical, to output first encoded data into which the first input data is encoded by the encoder and to output, successively to the first encoded data, a special code as second encoded data into which the second input data is encoded, 
   the decoder comprises:
 a decoder configured to decode according to a clock embedded encoding method; 
 a memory configured to retain decoded data produced by the decoder; and 
 a state decision circuit configured to, in response to successive undecoded first and second encoded data where the second encoded data is a special code, output first decoded data into which the first encoded data is decoded by the decoder and output data identical to the first decoded data and retained by the memory, as second decoded data into which the second encoded data is decoded, 
   wherein the special code is not stipulated in the clock embedded encoding method and exhibits a higher bit change rate than that produced according to the predetermined encoding method does.   
     
     
         18 . The transmission system according to  claim 17 , wherein in response to the first and second input data being different from each other, the comparator outputs, as the second encoded data, data into which the second input data is encoded by the encoder. 
     
     
         19 . The transmission system according to  claim 17 , wherein in response to the second encoded data being different from the special code, the state decision circuit outputs, as the second decoded data, data into which the second encoded data is decoded by the decoder.