Flash Memory for Code and Data Storage

Abstract

A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

1 . (canceled) 
     
     
         2 . A flash memory comprising:
 a first NAND flash memory array having a first read speed and a first storage capacity;   a second NAND flash memory array having a second read speed and a second storage capacity, the first read speed being faster than the second read speed, and the second storage capacity being greater than the first storage capacity; and   a multi-input/output Serial Peripheral Interface coupled to the first and second NAND flash memory arrays and having a plurality of configurable pins configurable as a single Serial Peripheral Interface or as a quad Serial Peripheral Interface to provide access to the first and second NAND flash memory arrays.   
     
     
         3 . A flash memory as in  claim 2  wherein the first NAND flash memory array comprises strings of stacked NAND cells having 2, 4, 8 or 16 word lines per string. 
     
     
         4 . A flash memory as in  claim 2  wherein the first NAND flash memory array is segmented into multiple arrays. 
     
     
         5 . A flash memory as in  claim 2  wherein:
 the first NAND flash memory array comprises strings of stacked NAND cells, and 
 the strings of stacked NAND cells in the first NAND flash memory array comprise plural bit lines per cell. 
 
     
     
         6 . A flash memory as in  claim 2  wherein:
 the first NAND flash memory array comprises strings of stacked NAND cells having four word lines per string, and 
 the strings of stacked NAND cells in the first NAND flash memory array comprise plural bit lines per cell. 
 
     
     
         7 . A flash memory as in  claim 2  wherein the multi-input/output Serial Peripheral Interface is further configurable as a dual Serial Peripheral Interface to provide access to the first and second NAND flash memory arrays. 
     
     
         8 . A flash memory comprising:
 a first chip comprising:
 a first NAND flash memory array having a first read speed and a first storage capacity; and 
 a first multi-input/output Serial Peripheral Interface coupled to the first NAND flash memory array and having a plurality of configurable pins configurable as a single Serial Peripheral Interface or as a quad Serial Peripheral Interface to provide access to the first NAND flash memory array; 
   a second chip comprising:
 a second NAND flash memory array having a second read speed and a second storage capacity, the first read speed being faster than the second read speed, and the second storage capacity being greater than the first storage capacity; and 
 a second multi-input/output Serial Peripheral Interface coupled to the second NAND flash memory array and having a plurality of configurable pins configurable as a single Serial Peripheral Interface or as a quad Serial Peripheral Interface in the same manner as the configurable pins of the first multi-input/output Serial Peripheral Interface to provide access to the second NAND flash memory array; and 
   a multi-chip package containing the first chip and the second chip and comprising a plurality of pins mounted thereon, at least some of the pins of the multi-chip package being configurable pins, and each of the configurable pins of the multi-chip package being coupled to respective same-type configurable pins of the first and second multi-input/output Serial Peripheral Interfaces.   
     
     
         9 . A flash memory as in  claim 8  wherein the pins of the multi-chip package consist of eight pins common to pins of both the first multi-input/output Serial Peripheral Interface and the second multi-input/output Serial Peripheral Interface, the eight pins respectively being a power pin, a ground pin, a clock pin, a chip select pin, a configurable hold or input/output pin, a configurable write-protect or input/output pin, a configurable data out or input/output pin, and a configurable data in or input/output pin. 
     
     
         10 . A flash memory as in  claim 9  wherein:
 the first multi-input/output Serial Peripheral Interface is further configurable as a dual Serial Peripheral Interface; and 
 the second multi-input/output Serial Peripheral Interface is further configurable as a dual Serial Peripheral Interface; and 
 the pins of the multi-chip package are further configurable in a dual serial configuration to provide access to the first NAND flash memory array and to the second NAND flash memory array.