Controllable storage elements for an ic

Abstract

An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC.

1 - 14 . (canceled) 
     
     
         15 . An integrated circuit (“IC”) comprising:
 a) a plurality of configurable logic circuits for configurably performing computations; 
 b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; and 
 c) a plurality of configurable storage circuits, each of the plurality of configurable storage circuits for configurably storing a signal that the configurable storage circuit receives; and 
 d) a plurality of clocked storage circuits, each clocked storage circuit receiving a periodic clock signal for directing the storage of the signals received by the clocked storage circuit. 
 
     
     
         16 . The IC of  claim 15 , wherein each of the plurality of clocked storage circuits comprises at least one input, at least one output, and a series of clocked delay elements connected serially. 
     
     
         17 . The IC of  claim 16 , wherein during each particular clock cycle, each particular clocked storage circuit (i) stores a signal provided at said input and (ii) supplies, at said output, a signal stored during a first clock cycle prior to the particular clock cycle. 
     
     
         18 . The IC of  claim 17 , wherein the first clock cycle occurs two clock cycles before the particular clock cycle. 
     
     
         19 . The IC of  claim 17 , wherein the first clock cycle occurs four clock cycles before the particular clock cycle. 
     
     
         20 . The IC of  claim 15 , wherein the configurable circuits are arranged in a particular arrangement, each of a group of the circuits comprising a plurality of inputs and at least one output. 
     
     
         21 . The IC of  claim 20 , wherein each particular group of configurable circuits in the arrangement further comprises at least one of said configurable storage circuits and at least one of said clocked storage circuits. 
     
     
         22 . The IC of  claim 15  further comprising a configurable routing fabric that is formed at least partially by a plurality of the configurable interconnect circuits, a plurality of the configurable storage circuits, and a plurality of the clocked storage circuits. 
     
     
         23 . An integrated circuit (“IC”) comprising:
 a) a plurality of configurable logic circuits for configurably performing logic operations; 
 b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; 
 c) a plurality of controllable storage circuits, each controllable storage circuit comprising:
 i) a controllable interconnect circuit for controllably passing signals to and from circuits of the IC; and 
 ii) a plurality of clocked delay elements connected serially with an output of each but the last delay element connected to an input of a subsequent delay element,
 wherein an output of each of at least two delay elements further connects to each of at least two inputs of the controllable interconnect circuit. 
 
 
 
     
     
         24 . The IC of  claim 23 , wherein the controllable interconnect circuit comprises a set of inputs, a set of select lines, and at least one output, wherein the controllable interconnect circuit selects an input from the set of inputs based on data supplied to the set of select lines. 
     
     
         25 . The IC of  claim 24 , wherein the controllable interconnect circuit is a configurable interconnect circuit that selects an input from the set of inputs based on a configuration data supplied to the set of select lines. 
     
     
         26 . The IC of  claim 24 , wherein the controllable interconnect circuit selects an input from the set of inputs based on a user design data supplied to the set of select lines. 
     
     
         27 . The IC of  claim 24 , wherein the controllable interconnect circuit is a hybrid interconnect circuit that selects an input from the set of inputs based on at least one of a configuration data and a user design data supplied to the set of select lines. 
     
     
         28 . The IC of  claim 23  further comprising a configurable routing fabric that is formed at least partially by a plurality of the configurable interconnect circuits and a plurality of the controllable storage circuits. 
     
     
         29 . The IC of  claim 23 , wherein an input of the first delay element is an input of the controllable storage circuit and an output of the controllable interconnect circuit is an output of the controllable storage circuit. 
     
     
         30 . The IC of  claim 23 , wherein:
 the plurality of clocked delay elements comprises four clocked delay elements,   the output of the second clocked delay element is connected to a first input of the controllable interconnect circuit, and   an output of the fourth clocked delay element is connected to a second input of the controllable interconnect circuit.   
     
     
         31 . An integrated circuit (“IC”) comprising a plurality of configurable clocked storage elements, each configurable clocked storage element comprising a set of clocked delay elements connected sequentially, each clocked delay element comprising at least one input and at least one output,
 wherein, during each particular clock cycle, the configurable clocked storage element receives a configuration data signal that controls whether the configurable clocked storage element stores a signal that the configurable clocked storage element receives and whether the configurable clocked storage element passes a signal that the configurable clocked storage element received during a clock cycle prior to the particular clock cycle. 
 
     
     
         32 . The IC of  claim 31  further comprising:
 a) a plurality of configurable logic circuits for configurably performing logic operations; and 
 b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits. 
 
     
     
         33 . The IC of  claim 32 , wherein:
 the configurable logic circuits are reconfigurable logic circuits,   the configurable interconnect circuits are reconfigurable interconnect circuits,   the configurable clocked storage elements are reconfigurable clocked storage elements, and   the particular clock cycle and the clock cycle prior to the particular clock cycle are different reconfiguration cycles.