Amplifier circuit

Abstract

According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.

What is claimed is: 
     
         1 . An amplifier circuit, comprising:
 an input transistor;   a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and   a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.   
     
     
         2 . The amplifier circuit of  claim 1 , wherein the protective circuit includes:
 a first MOS transistor that is diode-connected; and   a second MOS transistor disposed in parallel with the first MOS transistor and diode-connected in a reverse direction with respect to the first MOS transistor.   
     
     
         3 . The amplifier circuit of  claim 2 , wherein a source of the first MOS transistor and a drain of the second MOS transistor are connected to a variable bias voltage. 
     
     
         4 . The amplifier circuit of  claim 2 , wherein a source of the first MOS transistor and a drain of the second MOS transistor are connected to the bias voltage, and
 a body terminal of the first MOS transistor and a body terminal of the second MOS transistor are connected to a variable bias voltage.   
     
     
         5 . The amplifier circuit of  claim 1 , wherein the protective circuit includes:
 a first MOS transistor group including a plurality of MOS transistors disposed in series, respective MOS transistors being diode-connected in the same direction;   a second MOS transistor group disposed in parallel with the first MOS transistor group and including a plurality of MOS transistors disposed in series, respective MOS transistors being diode-connected in a reverse direction with respect to the respective MOS transistors included in the first MOS transistor group; and   a connection control unit controlling a short-circuit of sources and drains of the respective MOS transistors included in the first MOS transistor group and the second MOS transistor group.   
     
     
         6 . The amplifier circuit of  claim 2 , wherein the protective circuit further includes:
 a first source follower circuit including a third transistor having a drain connected to a predetermined voltage; and   a second source follower circuit including a fourth transistor having a drain connected to the predetermined voltage,   wherein the drain of the third MOS transistor is connected to a gate of the first MOS transistor,   the drain of the fourth MOS transistor is connected to a gate of the second MOS transistor, and   the third MOS transistor and the fourth MOS transistor has gates connected to a variable bias voltage.