High current capable access device for three-dimensional solid-state memory

Abstract

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

What is claimed is: 
     
         1 . A three-dimensional memory array, comprising:
 a plurality of first memory cells, each first memory cell coupled to a first three terminal device, wherein the first three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector;   a plurality of second memory cells, each second memory cell coupled to a second three terminal device, wherein the second three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector; and   a plurality of third memory cells, each third memory cell coupled to a third three terminal device, wherein the third three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector, and wherein first electrical connector of the first three terminal device is coupled to the first electrical connector of the second three terminal device and the third three terminal device.   
     
     
         2 . The three-dimensional memory array of  claim 1 , further comprising:
 a plurality of fourth memory cells, each fourth memory cell coupled to a fourth three terminal device, wherein the fourth three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector.   
     
     
         3 . The three-dimensional memory array of  claim 2 , wherein the first electrical connector of the fourth three terminal device is coupled to the first electrical connector of the third three terminal device. 
     
     
         4 . The three-dimensional memory array of  claim 3 , wherein second electrical connector of each of the first three terminal device, the second three terminal device, the third three terminal device and the fourth three terminal device are parallel. 
     
     
         5 . The three-terminal memory array of  claim 4 , wherein the third connector of each of the first three terminal device, the second three terminal device, the third three terminal device and the fourth three terminal device are parallel. 
     
     
         6 . The three-dimensional memory array of  claim 5 , wherein the first three terminal device is a MESFET. 
     
     
         7 . The three-dimensional memory array of  claim 6 , wherein the second three terminal device is a MESFET. 
     
     
         8 . The three-dimensional memory array of  claim 7 , wherein the third three terminal device is a MESFET. 
     
     
         9 . The three-dimensional memory array of  claim 8 , wherein the fourth three terminal device is a MESFET. 
     
     
         10 . The three-dimensional memory array of  claim 9 , wherein each first memory cell is a phase change memory cell. 
     
     
         11 . The three-dimensional memory array of  claim 10 , wherein each second memory cell is a phase change memory cell. 
     
     
         12 . The three-dimensional memory array of  claim 11 , wherein each third memory cell is a phase change memory cell. 
     
     
         13 . The three-dimensional memory array of  claim 12 , wherein each fourth memory cell is a phase change memory cell. 
     
     
         14 . The three-dimensional memory array of  claim 9 , wherein each first memory cell is a tunnel magneto-resistive cell. 
     
     
         15 . The three-dimensional memory array of  claim 14 , wherein each second memory cell is a tunnel magneto-resistive cell. 
     
     
         16 . The three-dimensional memory array of  claim 15 , wherein each third memory cell is a tunnel magneto-resistive cell. 
     
     
         17 . The three-dimensional memory array of  claim 16 , wherein each fourth memory cell is a tunnel magneto-resistive cell. 
     
     
         18 . A three-dimensional memory array, comprising:
 a plurality of first memory cells, each first memory cell coupled to a first three terminal device, wherein the first three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector;   a plurality of second memory cells, each second memory cell coupled to a second three terminal device, wherein the second three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector; and   a plurality of third memory cells, each third memory cell coupled to a third three terminal device, wherein the third three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector, and wherein first electrical connector of the first three terminal device is coupled to the first electrical connector of the second three terminal device and the third three terminal device, wherein second electrical connector of each of the first three terminal device, the second three terminal device, the third three terminal device and the fourth three terminal device are parallel.   
     
     
         19 . The three-terminal memory array of  claim 18 , wherein the third connector of each of the first three terminal device, the second three terminal device, the third three terminal device and the fourth three terminal device are parallel. 
     
     
         20 . A three-dimensional memory array, comprising:
 a plurality of first memory cells, each first memory cell coupled to a first three terminal device, wherein the first three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector;   a plurality of second memory cells, each second memory cell coupled to a second three terminal device, wherein the second three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector; and   a plurality of third memory cells, each third memory cell coupled to a third three terminal device, wherein the third three terminal device is coupled to a first electrical connector, a second electrical connector and a third electrical connector, and wherein first electrical connector of the first three terminal device is coupled to the first electrical connector of the second three terminal device and the third three terminal device, wherein the first three terminal device is a MESFET.