Memory device and methods of forming memory device and semiconductor device

Abstract

A method of forming a memory device is provided. A first conductive layer is formed on a substrate. The first conductive layer is patterned to form at least two trenches extending along a first direction therein. An insulating layer is formed on surfaces of the trenches and on a surface of the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form at least one control gate extending along a second direction different from the first direction. The first conductive layer is patterned to form at least one floating gate below the control gate and to form a select gate adjacent to the control gate.

What is claimed is: 
     
         1 . A method of forming a memory device, comprising:
 forming a first conductive layer on a substrate;   patterning the first conductive layer to form at least two trenches therein, wherein the trenches extend along a first direction;   forming an insulating layer on surfaces of the trenches and on a surface of the first conductive layer;   forming a second conductive layer on the insulating layer;   patterning the second conductive layer to form at least one control gate extending along a second direction different from the first direction; and   patterning the first conductive layer to form at least one floating gate below the control gate and to form a select gate adjacent to the control gate.   
     
     
         2 . The method of  claim 1 , wherein the step of patterning the first conductive layer to form the trenches comprises:
 forming a first photoresist layer on the first conductive layer;   removing a first portion of the first conductive layer by using the first photoresist layer as a mask; and   removing the first photoresist layer.   
     
     
         3 . The method of  claim 1 , wherein the step of patterning the second conductive layer to form the control gate comprises:
 forming a hard mask layer and a second photoresist layer on the second conductive layer;   removing portions of the hard mask layer, the second conductive layer and the insulating layer by using the second photoresist layer as mask, so as to form at least one stacked structure on the first conductive layer, wherein the stacked structure comprises, from bottom to top, an inter-gate insulating layer, the control gate and a hard mask pattern; and   removing the second photoresist layer.   
     
     
         4 . The method of  claim 3 , further comprising forming a first spacer on a sidewall of the stacked structure. 
     
     
         5 . The method of  claim 4 , wherein the step of patterning the first conductive layer to form the floating gate and the select gate comprises:
 forming a third photoresist layer on the first conductive layer adjacent to the stacked structure;   removing a second portion of the first conductive layer by using the hard mask pattern and the first spacer as a mask, so as to form the floating gate below the control gate; and   removing a third portion of the first conductive layer by using the third photoresist layer as a mask, so as to form the select gate adjacent to the control gate; and   removing the third photoresist layer.   
     
     
         6 . The method of  claim 1 , further comprising forming an interfacial layer on the substrate before the step of forming the first conductive layer. 
     
     
         7 . The method of  claim 1 , further comprising forming a plurality of doped regions in the substrate after the step of patterning the first conductive layer to form the floating gate and the select gate. 
     
     
         8 . The method of  claim 7 , wherein the floating gate and the doped regions have different conductivity types. 
     
     
         9 . The method of  claim 8 , wherein the insulating layer comprises a single layer or a multi-layer structure. 
     
     
         10 . A method of forming a semiconductor device, comprising:
 forming at least two trenches, extending along a first direction, in a material layer;   forming at least one stripe-shaped pattern, extending along a second direction different from the first direction, on the material layer; and   removing a portion of the material layer by using the stripe-shaped pattern as a mask and simultaneously removing another portion of the material layer.   
     
     
         11 . The method of  claim 10 , wherein each of the material layer and the stripe-shaped pattern comprises a conductive material. 
     
     
         12 . The method of  claim 11 , wherein the material layer and the stripe-shaped pattern are separated from each other by an insulating layer. 
     
     
         13 . The method of  claim 10 , wherein the another portion of the material layer is removed by using a photoresist layer as a mask. 
     
     
         14 . A memory device, comprising:
 a control gate, disposed on a substrate;   a plurality of floating gates, disposed between the control gate and the substrate, wherein a width of each floating gate is greater than a width of the control gate;   an inter-gate insulating layer, disposed between the control gate and each of the floating gates; and   a select gate, disposed on the substrate adjacent to the control gate.   
     
     
         15 . The memory device of  claim 14 , further comprising:
 a plurality of tunnelling dielectric layers, respectively disposed between the floating gates and the substrate;   a gate dielectric layer, disposed between the select gate and the substrate; and   a plurality of doped regions, disposed in the substrate adjacent to the floating gate and the select gate.   
     
     
         16 . The memory device of  claim 15 , wherein the floating gate and the doped regions have different conductivity types. 
     
     
         17 . The memory device of  claim 15 , wherein no doped region is present in the substrate between the floating gate and the select gate. 
     
     
         18 . The memory device of  claim 14 , further comprising a spacer disposed on the floating gates and on a sidewall of the control gate. 
     
     
         19 . The memory device of  claim 14 , wherein the control gate further extends into gaps between two adjacent floating gates. 
     
     
         20 . The memory device of  claim 14 , wherein the inter-gate insulating layer is a single layer or a multi-layer structure.