Non-volatile memory device and method of manufacturing the same

Abstract

A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.

What is claimed is: 
     
         1 . A method of manufacturing a non-volatile memory device, comprising steps of:
 forming a trench on a substrate and an active region defined by the trench, a sidewall of the trench being straight from a top to a bottom of the trench such that a width of the trench decreases with increasing depth;   forming a device isolation pattern positioned at a lower portion of the trench;   forming a memory cell layer including insulation layers of a tunnel insulation layer, a trap insulation layer and a blocking dielectric layer wherein the insulation layers are sequentially stacked on the active region;   forming one of the insulation layers extending from the active region toward the device isolation region to enclose top of an air gap conformal to the straight sidewall of the trench, bottom of the air gap being defined by a layer other than that of the top; and   forming a control gate electrode positioned on the cell structure.   
     
     
         2 . The method of  claim 1 , wherein the one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap. 
     
     
         3 . The method of  claim 1 , wherein the step of forming one of the insulation layers extending is carried out with the substrate tilted at a first tilt angle. 
     
     
         4 . The method of  claim 3 , wherein the steps of forming one of the insulation layers is further carried out with the substrate tilted at a second tilt angle. 
     
     
         5 . A non-volatile memory device comprising:
 a substrate having an active region defined by a device isolation region, the device isolation region having a trench and an air gap;   a device isolation pattern positioned at a lower portion of the trench;   a memory cell layer including insulation layers of a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region, one of the insulation layers being discontinuous across the active region and the device isolation region and one of other insulation layers on the discontinuous insulation layer being continuous across the active region and the device isolation region and covering the air gap; and   a control gate electrode positioned on the cell structure.   
     
     
         6 . The non-volatile memory device of  claim 5 , wherein the trap insulation layer is discontinuous and the blocking insulation layer on the trap insulation layer on the trap insulation layer is continuous across the active region and the device isolation region such that the air gap is covered with the blocking insulation layer. 
     
     
         7 . The non-volatile memory device of  claim 5 , wherein the tunnel insulation layer is discontinuous and the trap insulation layer on the tunnel insulation layer on the trap insulation layer is continuous across the active region and the device isolation region such that the air gap is covered with the trap insulation layer.