Semiconductor device with refresh control circuit

Abstract

In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a memory cell array comprising a plurality of word lines, a plurality of bit lines each intersecting the word lines, and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines; and   a row-based control circuit taking an active state, to access the memory cell array, and a standby state, to suspend accessing the memory cell array, the row-based control circuit being equipped with a current reduction circuit to reduce a power consumption during the standby state and configured to respond to a refresh command to take the active state at least twice with an intervention of the standby state therebetween, the row-based control circuit being further configured to activate two or more of the word lines each time the active state is being taken so that each of the memory cells coupled to the two or more of the word lines can be refreshed.