Multi-core processor system, memory controller control method, and computer product

Abstract

A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.

What is claimed is: 
     
         1 . A multi-core processor system comprising a plurality of cores and a shared memory storing a parallel degree information including a software executed in parallel by a plurality of cores of the plurality of cores and a number of cores to which the software is assigned when the software is executed in parallel, wherein
 a first core of the plurality of cores is configured to:   determine a core to which a software to be executed is to be assigned, from the plurality of cores, based on the parallel degree information and execution load of each of the plurality of cores.   
     
     
         2 . A control method for controlling a multi-core processor system that comprises a plurality of cores and a shared memory storing a parallel degree information including a software executed in parallel by a plurality of cores of the plurality of cores and a number of cores to which the software is assigned when the software is executed in parallel, wherein
 determining, by the multi-core processor system, a core to which the software to be executed is to be assigned, from the plurality of cores, based on the parallel degree information and execution load of each of the plurality of cores.